New Yorke chip in hardware

[BruceH]

Following on from the "New Yorke" thread in the other forum, I wondered how feasible it would be to get Google to make it for us?

[mfleming]

Perhaps Monte's NEWT microprocessor in the 41CL for starters? Even with the process node and die size restrictions, you should be able to get all of RAM memory, plus perhaps Timer, Printer, and HP-IL peripherals.

I'll take one!

[Jonathan Busby]

(07-04-2020 11:31 PM)BruceH Wrote:  Following on from the "New Yorke" thread in the other forum, I wondered how feasible it would be to get Google to make it for us?

Well, I really don't think Google's offer is worth it. It's *much* easier to use a low power FPGA, such as one from Microchip Technologies or Lattice Semiconductor.

With an FPGA you have most of the capabilities of something like a "standard cell" ASIC, but with the ability to re-configure the FPGA to any circuit / netlist you want ( within limits ) without having to actually fab anything.

Modern FPGAs are quite powerful and feature rich. Take for example Xilinx : With their "Artix-7" "low power" FPGA family, you get, depending on the model, several Mbits of block and distributed RAM, multiple configurable clock domains with Digital Clock Managers, configurable I/O, DSP functionality via DSP blocks / "slices", and much more.

The problem with Xilinx "low power" FPGAs is that Xilinx considers "low power" to be in the ~25 milli-amp range for *quiescent* current draw, not to mention active current draw ( And this makes me sad because a lot of my designs use Xilinx FPGAs ). If you're willing to sacrifice some functionality and features, then my choice would be the Lattice Semiconductor iCE40 UltraLite UL1K FPGA. It's based on 28 nm process technology with about a 35 µA quiescent current draw, so it blows away Google's 130 nm offering. The logic cells are somewhat simpler than Xilinx : You get a flip-flop with an enable and clock-enable input, one 4-input LUT and fast carry logic. The FPGA also has around 56 kbits ( ~6.84 kBytes ) of block RAM, configurable I/O blocks and two oscillators ( It lacks Xilinx's powerful DCMs ).

With the Google offering, Google has to *select* your RTL code and it has to be open source. Also, even if they do select your code, it has to be in Git repo ( I prefer SVN ) and they'll only fab up to about 100 parts.

With the Lattice FPGA solution, you get free EDA software ( Lattice Diamond ) and the dev board only costs a little over $100 USD ( of which I have a few ).

IMHO, Google's offering is just a publicity stunt

Regards,

Jonathan

[EdS2]

I too am finding it hard to see applicability for my interests in Google's offer of free chips: FPGAs do tick a lot of boxes. It's an attractive offer on the face of it, but I was reminded how very involved and exacting the chip design process is. You'd very likely want to bring up your design on an FPGA before finalising your design anyway.

The very low power Lattice offerings are a good find!

Two disadvantages for me: only available in BGA packages, and not 5V tolerant. These are of course minor points, especially for a new standalone calculator-type of application.

An advantage (for me) of Lattice's ICE40 range, hopefully including these low power ones: an open source toolchain is available.

[Jonathan Busby]

(07-16-2020 08:02 AM)EdS2 Wrote:  Two disadvantages for me: only available in BGA packages, and not 5V tolerant. These are of course minor points, especially for a new standalone calculator-type of application.

Well, this can be easily gotten around by using a small daughterboard and a μC voltage regulator and supervisory IC. The power supplies in eg. the HP48G series and HP48S series and older HP calculators are not only ancient, but not that efficient compared to a modern tiny voltage regulator chip.

Quote:An advantage (for me) of Lattice's ICE40 range, hopefully including these low power ones: an open source toolchain is available.

Unfortunately ( for me ), said toolchain doesn't yet support the Lattice iCE40 Ultra and UltraLite FPGAs, which I've been using -- I have to use Aldec's proprietary Active-HDL simulator for timing simulation and post place-and-route-simulation and Lattice's proprietary iCEcube2 EDA tool for synthesis, place-and-route, bitstream generation and device programming Also, the Active-HDL version that is packaged with Lattice's iCEcube2 EDA software is crippled with respect to its performance and some language features such as UVM SystemC and SystemVerilog and it's only 32-bit and only runs on Windows -- if you want the uncrippled version, you have to pay $2K USD per year . I usually use Verilator though for pre-synthesis simulation of the synthesizeable constructs of SystemVerilog and Verilog-2001. Verilator is not only opensource but it's *much*, *much* faster than "Active-HDL". Still, I have to use Active-HDL for the timing and post place-and-route simulation.

Regards,

Jonathan