New Saturn asm "add loop" benchmark for the HP48G
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11-04-2023, 02:20 PM
(This post was last modified: 11-05-2023 02:15 AM by Jonathan Busby.)
Post: #18
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RE: New Saturn asm "add loop" benchmark for the HP48G
For all practical purposes, only the very inner portion of the add loop need be investigated since the outer portion of the loop is only executed about four times :
Code: l1 C=C+1 A The "GONC" branch instruction takes up the bulk of the CPU time. When the above code starts on an odd address, a total of around 5̶ ( wrong ) 10 additional cycles are required. If X is the total cycle time of the above inner loop, then we have : \(\displaystyle \dfrac{(X + 10)}{X} \approx \dfrac{8765045}{4383185} \) ( EDIT #1 : "10" was "5" above ) then \(\displaystyle X \approx \dfrac{-10}{1 - \left (\dfrac{8765045}{4383185} \right )} \) ( EDIT #1 : "-10" was "-5" above ) \(\displaystyle \approx 10 \) ( EDIT #1 : "10" was "5" above ) The above is nonsensical : to get the speedup indicated by the aberrant count, the whole inner loop would have to take just 5̶ 10 cycles, which is impossible. I think, therefore, we can conclude that the speedup, if it isn't a bug in my code, is not due to memory address parity. Regards, Jonathan EDIT #1 : My calculation is in error ( although it doesn't change the conclusion ) since I mistakenly divided the values from Cycles du Saturn by two -- it's been corrected. Aeternitas modo est. Longa non est, paene nil. |
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