Question regarding HP41C Power Up Status circuit

[Jonathan Busby]

Well, it's been a long time since I've posted anything here. I think my last post was in early 2003, so that's about 15 years .

To get to the point, I've been looking for a circuit described in the HP41C technical hardware reference manual. Specifically, it's the Power Up Status OR "PUS" circuit in the 1LF6 chip. According to the manual "PUS uses a two threshold detection scheme coupled to a ratioed flip-flop designed to power up in a known state." I'd like to know how this circuit works but the manual says "Refer to the 1LF6 logic diagram for a full PUS circuit schematic." The only problem is that I've done a thorough search and I can't find said schematic. Does anyone know where the schematic is?

Thanks,

Jonathan

[cruff]

The diagram part number is given as E-1LF6-9001-50 in the timer chip detailed description, but a Google search does not turn up any hits.

[AndiGer]

Jonathan,
Welcome back ...
What's that technical hardware reference manual you mention? I can't find anything similar in the museum's DVD contents.

[Jonathan Busby]

(06-14-2018 03:35 AM)AndiGer Wrote:  Jonathan,
Welcome back ...

Thanks and you're welcome!

Quote:What's that technical hardware reference manual you mention? I can't find anything similar in the museum's DVD contents.

Sorry for not providing this info in my post. I have version 8.0 of the museum's documents on a USB flash drive. The file is located in the "Service Manuals & Internals" section with a name of "hp41cpu.pdf" and a path of "/data/cd11/intern/hp41cpu.pdf". It's entitled "HP-41C CPU, Display Driver, HP-IL, Data Storage, Timer IC, and Interface IC Specifications" . The portion mentioning the PUS circuit is in section 5.1.6 .

Regards,

Jonathan