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+--- Thread: When ISZ/DSZ > ISG/DSE (/thread-13017.html)
When ISZ/DSZ > ISG/DSE - Gene - 05-23-2019 11:51 PM
Ran across something interesting (to me at least) in an HP KeyNotes issue.
The situation was on the HP-67, the I register contained either a zero or one. Goal was to use ISZ/DSZ to switch it. Think of it as a brain-teaser:
"The X register contains either a zero or one. Flip the value without using any digit keys or X=? test conditionals."
The solution presented was...
ISZ
DSZ
DSZ
ISZ
which works. Then I started thinking. That's hard to do on the HP41 style structure.
ISG won't work here. Thoughts?
Try it on your HP67 or an emulator and help me think through how to do it this way on an HP41. No X=Y? or X=0? conditionals allowed. :-)
RE: When ISZ/DSZ > ISG/DSE - Thomas Okken - 05-24-2019 12:00 AM
SIGN
LASTX
-
RE: When ISZ/DSZ > ISG/DSE - Gene - 05-24-2019 12:44 AM
Which certainly works on X as I laid it out. Thomas is a master. :-)
What proposals for a value in a memory register?
RE: When ISZ/DSZ > ISG/DSE - rprosperi - 05-24-2019 01:08 AM
(05-24-2019 12:00 AM)Thomas Okken Wrote: SIGN
LASTX
-
Awesome. And elegant!
RE: When ISZ/DSZ > ISG/DSE - Gerson W. Barbosa - 05-24-2019 02:59 AM
ACOS
SIN
By Andrés Rodríguez, I think.
RE: When ISZ/DSZ > ISG/DSE - Paul Dale - 05-24-2019 04:10 AM
On the 34S, I think the minimal real mode solution would be:
Code:
NOTThe 34S has both flavours of increment (i.e. ISG and ISZ).
Pauli
RE: When ISZ/DSZ > ISG/DSE - Andres - 05-24-2019 12:59 PM
Thank you Gerson for remembering this old answer from me to an old similar challenge!
RE: When ISZ/DSZ > ISG/DSE - Didier Lachieze - 05-24-2019 01:31 PM
(05-24-2019 12:44 AM)Gene Wrote: What proposals for a value in a memory register?
Here is a proposal for a value in memory register 01 that keeps the stack and lastX unchanged:
Code:
X<> 01
DSE X
CHS
CHS
X<> 01RE: When ISZ/DSZ > ISG/DSE - Gerson W. Barbosa - 05-24-2019 02:00 PM
CHS
ISG X
Two steps also, but Andrés Rodríguez’s solution should be still one byte shorter.
RE: When ISZ/DSZ > ISG/DSE - Thomas Okken - 05-24-2019 02:35 PM
(05-24-2019 02:00 PM)Gerson W. Barbosa Wrote: CHS
ISG X
Two steps also, but Andrés Rodríguez’s solution should be still one byte shorter.
Andrés' solution looks unbeatable on size, but it is slower. Not a lot slower, to be honest, since it takes advantage of special cases in ACOS and SIN, so it really is quite brilliant. I wish I had thought of it.
CHS ISG X is flawed because the ISG skips the next instruction in the 0 → 1 case...
RE: When ISZ/DSZ > ISG/DSE - Gerson W. Barbosa - 05-24-2019 04:02 PM
(05-24-2019 02:35 PM)Thomas Okken Wrote: CHS ISG X is flawed because the ISG skips the next instruction in the 0 → 1 case...
Yes, I am aware of that. Anyway, the following works on both the 41 and 42:
01 LBL “W”
02 CHS
03 ISG X
04 END
0 XEQ W -> 1
XEQ W -> 0
XEQ W -> 1
and so on...
RE: When ISZ/DSZ > ISG/DSE - Andres - 05-28-2019 09:41 PM
Thomas, Gerson,
Your generous (and mostly undeserved) comments about [ACOS | SIN] made my day. Thank you!!
RE: When ISZ/DSZ > ISG/DSE - Gerson W. Barbosa - 05-29-2019 12:33 AM
(05-28-2019 09:41 PM)Andres Wrote: Thomas, Gerson,
Your generous (and mostly undeserved) comments about [ACOS | SIN] made my day. Thank you!!
You are most welcome!
Besides, unto Andrés what belongs to Andrés! :-)
Here it is, exactly fourteen years ago now:
A tiny solution for the 0<>1 toggle