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+--- Thread: SR-50/51 vs RPN (/thread-17073.html)
SR-50/51 vs RPN - Matt Agajanian - 06-07-2021 07:15 PM
Hi all.
While HP has maintained RPN, it seems to me that the Sum of Product logic in the SR-50/51 would be more cumbersome in comparison.
With the way the Sum of Products hierarchy system plays out and with the absence of parentheses, I would think that the 50/51 would require a good chunk of equation rearrangement and intermediate storage register use which would make RPN a more usable and efficient entry system.
Any thoughts?
RE: SR-50/51 vs RPN - Stevetuc - 06-07-2021 07:33 PM
(06-07-2021 07:15 PM)Matt Agajanian Wrote: Hi all.
While HP has maintained RPN, it seems to me that the Sum of Product logic in the SR-50/51 would be more cumbersome in comparison.
With the way the Sum of Products hierarchy system plays out and with the absence of parentheses, I would think that the 50/51 would require a good chunk of equation rearrangement and intermediate storage register use which would make RPN a more usable and efficient entry system.
Any thoughts?
I had an SR50 back in the day and it requires use of memory for product of sums and is more complex than rpn. There are some examples of this in the manual http://www.datamath.net/Manuals/SR-50_US.pdf
RE: SR-50/51 vs RPN - Steve Simpkin - 06-07-2021 07:49 PM
I agree that these early TI models without parenthesis keys were not easy to use on complex calculations. The mental gyrations needed for calculating parenthesis heavy formulas could be daunting if you didn't break down the equation into simpler subsets first. Even then, this may have required intermediate results to be written down and re-entered in order to solve some problems.
I have always thought that the reason they didn't implement parenthesis keys on these early models was because of transistor count. It takes approximately 4-6 MOS transistors to provide a bit of storage in these IC designs. If a register occupies about 56 bits (as in the early HP models) then that translates into approximately 200-300 transistors per register. The early MOS LSI IC designs in this era were often limited to around of 2000-6000 transistors per IC. The "cost" of adding 5-7 extra registers needed for a good parenthesis implementation on top of the existing working registers was probably just too great for these early TI models.
Conversly, HP models, with their RPN logic and a four level stack, were able to provide a workable entry system that allowed most problems to be solved without writing down intermittent results. The methods used to break down a problem and to work it from the inside out also had the added advantage of mimicking the methods you would have used to solve the problem with a pencil and paper (or a slide rule).