"New-Yorke" ?

[Jonathan Busby]

I'm one of the people who edits HP4x calculator, HP Saturn CPU, RPL, RPN and many, many other ( unrelated ) articles on Wikipedia. In the article about the HP Saturn CPU it's mentioned that :

Quote:"New-Yorke [....] HP 48GX prototype [...] 8 MHz, LCD controller, memory controller, UART and IR control. This was only made as an internal HP prototype and never released in the wild."

You can probably guess which user is me by my username attached to my edits

Anyways, as far as I can tell, and I have done *much* research, there are no verifiable sources that meet Wikipedia's standards in reference to the so called "New-Yorke" 8MHz HP Saturn based SoC prototype -- it seems to be either hearsay or a leak from the HP internal hardware design team.

Since there are no sources, I'd like to remove the material about the "New-Yorke" SoC from the HP Saturn CPU article, but, if anyone can point me to any verifiable sources, I'd be very much appreciative

Thanks,

Jonathan

[cyrille de brébisson]

Hello,

As far as I know, it was work done by the old calc division in corvalis.
I definitely heard talks about it when I was in Australia, but that chip never made it to manufacturing. I do not know why. People where not there anymore to continue the project and we had no HW experience...
It would have been nice to have for the 49/39 series...

Nevertheless, the later 50G arm based series were call the apple series because of the "new Yorke"...
At the time, now knowing what the "Yorke" stood for (even as I lived in Idaho by then!), "New Yorke" made me think of "the big apple", and I therefore decided to call the 50G/48GII++ (or whatever the name was) and 39GII+ by the name little, mid and big apple!

Someone like Jim Donneli might know more about the New Yorke.
If not real, it might be interesting to at least leave the statement in Wikipedia noted as an unverified anecdote that might be true or not, but is still part of the building of later calc history!

Cyrille

[Jonathan Busby]

(06-16-2020 05:48 AM)cyrille de brébisson Wrote:  Hello,

As far as I know, it was work done by the old calc division in corvalis.
I definitely heard talks about it when I was in Australia, but that chip never made it to manufacturing. I do not know why. People where not there anymore to continue the project and we had no HW experience...
It would have been nice to have for the 49/39 series...

Thanks for the reply! It's a shame that a 2x faster improved version of the Yorke SoC didn't even make it to silicon

Quote:Nevertheless, the later 50G arm based series were call the apple series because of the "new Yorke"...
At the time, now knowing what the "Yorke" stood for (even as I lived in Idaho by then!), "New Yorke" made me think of "the big apple", and I therefore decided to call the 50G/48GII++ (or whatever the name was) and 39GII+ by the name little, mid and big apple!

I didn't know this! Thanks for the info!

Quote:Someone like Jim Donneli might know more about the New Yorke.

Thanks very much for the information and suggestion Do you know how I might go about contacting Jim Donnelly about this?

Quote:If not real, it might be interesting to at least leave the statement in Wikipedia noted as an unverified anecdote that might be true or not, but is still part of the building of later calc history!

The problem is that it's official Wikipedia policy to remove unsourced statements and/or information, so, I'd need at least one reliable source to keep it in the article.

Quote:Cyrille

Regards,

Jonathan

[pinkman]

Quote:The problem is that it's official Wikipedia policy to remove unsourced statements and/or information, so, I'd need at least one reliable source to keep it in the article.

The URL of this thread is already one, since Cyrille is well know in the HP calc spheres. Enough for the Wikipedia policy?

[cyrille de brébisson]

Hello,

Here is what my memory tells me...
Note that we are talking about events that happened over 20 years ago... How reliable is memory after 20 years? I will try to add "qualifier" on various statements to give a "certitude level" for the various statements.

"New Yorke" as a project or a concept IS real. I heard about it when I joined the ACO (Australian Calculator Operation) in 1998. Since before joining the ACO I did not know about the "Yorke" chip (we did not have official HP data in France when I was younger, and we always refereed to the 48 CPU as the Saturn), I am prety damn sure that this memory is accurate....

Note: This project would have been started by the Corvalis team at a time when the Calculator group was part of the larger Singapore handheld group (Jordana and the like). The Singapore group did not having much interest in calculators (which where just added on top of their other stuff), so they did not do much about it, which is why the Corvalis group ended up being "discarded". Since silicon is long and expensive, it most likely explains why the project never made it pass the prototype stage.

New Yorke was definitely a project to speed up the CPU to 8Mhz (from the original 4Mhz). I remember that also with high certainty.

I have vague recollections actually seeing a 48 with said faster chip. BUT I would not swear to that memory. It might be just a figment of my imagination (or my wishes).
What I find disturbing in this memory is that, had we had such a calculator in our hands at the ACO, one of the 3 of us (Jean-Yves, Gerald or myself) would most likely have claimed it! and treasure it... Had I had it, I would most likely have unsolder the CPU and shoved it in my velvet black HP49G. I would have keept that chip in a special place and held on to it with all my geeky strength!
Jean-Yves might have been less inventive, but he definitely would have been very outspoken about it and showed it around a lot. I do not think that Gerald would have fought us for it, so I don't think that he would have ended up with it.
But I definitely do not have said calc and do not remember Jean-Yves having it. Which makes me think that it never made it to the ACO.
What might have happened is that it might have been in the hand of one of the Corvalis members (Jimm, Diana) who might have shown it to Jean-Yves, but not given it to him.
Hence I would have ended up with the knowledge of the existence, the project name a first hand account of the existence, but not the device itself.

I remember hearing that the main issue with the project was instability and low yields. This is also a relatively high certainty memory.

So, here you go, all the data that I can remember, "from the horse's mouth", for Wikipedia.

Add to this that the Arm based devices project names WERE based on my quirky, non-native English brain word association, makes the New Yorke part of calculator history, weather it actually made it past the design phase to prototype or not.

Cyrille de Brébisson, HP calculator engineer 1998-now (2020) <-- official signature and all for wikipedia!
Hope that helps!

[Jonathan Busby]

(06-16-2020 11:03 PM)pinkman Wrote:  The URL of this thread is already one, since Cyrille is well know in the HP calc spheres. Enough for the Wikipedia policy?

I don't make or control Wikipedia's rules, so there's no need to get testy -- I'm not being smug or anything; I'm just stating a fact The admins on Wikipedia might take Cyrille's statements as "original research", which is a big no-no on Wikipedia. Also, it might look like a conflict of interest on my part ( see here ).

The Wikipedia article rules regarding sources are listed below :

• https://en.wikipedia.org/wiki/Wikipedia:...d_Material
• https://en.wikipedia.org/wiki/Wikipedia:...nformation
• https://en.wikipedia.org/wiki/Wikipedia:Citing_sources
  

Thank you very much Cyrille for the information If you could put it into an article form and post it to the articles section then I'd be very appreciative I could also create an article on your behalf if you would sign it to give it your seal of approval for the purposes of Wikipedia's verifiability guidelines

If I understand what you wrote correctly, the 8MHz "New-Yorke" chip actually *did* make it to silicon, but there were problems with yields and quality. Is that correct?

Thanks again,

Regards,

Jonathan

[cyrille de brébisson]

Hello,

I have never done any wikipedia work, so I have no clue how to put things in article form.

The post above is my attempt at putting together all that I could remember, Should you put it in a suitable form, I would be more than happy to review it and give my "stamp of approval"!

Cyrille

[pinkman]

I can write this part of the article in Wikipedia and refer to this thread. There is no risk of any conflict, my last real work in Wikipedia was in 2012 about smart metering

[Jonathan Busby]

(06-18-2020 05:50 AM)cyrille de brébisson Wrote:  Hello,

I have never done any wikipedia work, so I have no clue how to put things in article form.

The post above is my attempt at putting together all that I could remember, Should you put it in a suitable form, I would be more than happy to review it and give my "stamp of approval"!

Cyrille

I actually meant "article" as in the "articles" section of the HP Museum forums -- I wasn't asking you to modify the actual Wikipedia article

I guess I'll go ahead and write it up as an HP Museum article in the articles forum, and then use that article as a reference on the Wikipedia page for the HP Saturn CPU, if that's OK with you

Regards,

Jonathan

[pinkman]

Ok I understand the COI: your contribution in Wikipedia will refer to your contribution in MoHPC.
You should not write the MoHPC article, let others do it, or Cyrille if he has the courage to do it.

[Jonathan Busby]

(06-18-2020 10:11 PM)pinkman Wrote:  Ok I understand the COI: your contribution in Wikipedia will refer to your contribution in MoHPC.
You should not write the MoHPC article, let others do it, or Cyrille if he has the courage to do it.

I already created the article. It's just a quoted block of text from Cyrille's post. I've used it to reference the "New-Yorke" text in the Wikipedia article. Also, I've added an explanation of the "Big Apple", "Mid Apple" and "Little Apple" code names in the same Wikipedia article.

The second reference is a "{{cite web| ...}}" reference to one of Cyrille's posts in this thread and the first reference is the a reference to the article in the MoHPC's article forum. I can change the first reference to just point to Cyrille's post, which I think I'll do now.

Regards,

Jonathan

[Jonathan Busby]

Well, I went ahead and deleted the MoHPC article and changed the Wikipedia article's reference for "New-Yorke" to point directly to Cyrille's post. I hope that is acceptable to everyone

Regards,

Jonathan

[EugeneNine]

Where is the Saturn architecture now? For example I started out with the 6502 and know its still made and supported by https://www.westerndesigncenter.com/wdc/

Did the Saturn survive anywhere else, is the IP still owned by HP?

[Steve Simpkin]

(06-18-2020 11:17 PM)EugeneNine Wrote:  Where is the Saturn architecture now? For example I started out with the 6502 and know its still made and supported by https://www.westerndesigncenter.com/wdc/

Did the Saturn survive anywhere else, is the IP still owned by HP?

As for the Saturn processor in the HP 49G, that was the last we ever saw of it. It lives now only in emulation...

https://www.youtube.com/watch?v=OcK8FLGx0fo

[Jonathan Busby]

(06-18-2020 11:17 PM)EugeneNine Wrote:  Where is the Saturn architecture now? For example I started out with the 6502 and know its still made and supported by https://www.westerndesigncenter.com/wdc/

Did the Saturn survive anywhere else, is the IP still owned by HP?

Well, AFAIK, the original discrete 1LF2 Saturn chip that was part of the HP71B went through a gradual evolution over the years and was eventually incorporated into SoCs like the "Lewis", "Clarke" and "Yorke" SoCs.

Since the original Corvallis designed HP Saturn CPU was designed around 1983 to 1984 or so, and since each version of the Saturn CPU was leveraged from the previous generation, I'd think that the chip was designed using schematic capture. I say this because the Verilog and VHDL HDLs were created circa 1983 to 1984 and weren't standardized ( at least at the time of their inception -- AFAIK VHDL was standardized around 1992 and Verilog around 1995 IIRC ) and were proprietary and they had yet to see widespread adoption when the original Saturn CPU was designed mostly because the HDLs in question had just been created ( I'm not even sure if Verilog or VHDL, circa 1983 to 1984, were even available for public consumption as the languages had just been created ). Also, even *if* the Saturn CPU design team made use of an HDL, at the time, Verilog and VHDL were only designed for *simulation* and *verification* -- not for actual *hardware synthesis*.

I'd imagine that the various schematic capture gate-level ( see here and here, if "gate-level" design for the CPU was even used to a significant extent compared to mapping a schematic capture netlist to a PLA ) and PLA netlists and also higher level top-down block oriented schematic designs that were meant for PLAs in discrete Saturn CPUs, or on the various SoCs with integrated Saturn CPUs, are "lost to the sands of time" *But*, what's important is that the Saturn ISA is well documented, so the Saturn can still live on in emulator ( or other ) form

Regards,

Jonathan

NOTE : This post has been edited with references to various technical terms for the layperson, more in-depth explanations, grammar and style fixups, and more details added. Also, some content has been removed as I felt it too early and and too personal to release now -- PM me if you want details

[Giuseppe Donnini]

The mere thought of using Wikipedia as a reliable source for information on the Saturn CPU hadn’t even begun to speculate about the merest possibility of crossing my mind...
But given the high expertise of its main author, I took the time to read the entire article, and would like to address a couple of issues:

In the chapter "Chipsets and applications" the different Saturn incarnations are classified according to their so-called "level", but it remains entirely unclear what is actually meant.


A.
In original HP publications, the term "level" is used exclusively to refer to the set of instructions available for a given CPU. In that sense, there are exactly three levels:

 
1. Level 0 referring to the instruction set of the original stand-alone Saturn CPU (1LF2).
    
2. Level 1 referring to the instruction set of the redesigned, and improved, stand-alone Saturn CPU (1LK7).
    
3. Level 2 referring to the instruction set of the further improved Saturn CPU as it first appeared in the Lewis IC (1LR2).
   

And that’s all. Later (non-virtual) Saturn processors, i.e. those built into the Sacajawea IC (1LR3), the Bert IC (1LU7), the Clarke IC (1LT8), and the Yorke IC (00048-80063) all use the same level 2 instruction set.

Here are some official HP sources corroborating this point:

• SASM.DOC, p. 15 (reflecting the 1LR2 state of development, despite having been officially distributed for the first time with the "HP-48 Software Development Tools"):
   
  "The Saturn CPU has three variations used in several products. The 1LF2 was used in the first versions of the HP-71B. The 1LK7 is a variation of the 1LF2 used in later versions of the HP-71B, the HP-18C, and the HP-28C. The 1LR2 is an integrated CPU/ROM/RAM/Display Driver IC. Each new version of the Saturn CPU added new instructions to the Saturn instruction set. Instructions available in all Saturn CPUs are referred to as "level 0" instructions. Instructions available in the 1LK7 and 1LR2 but not the 1LF2 are referred to as "level 1" instructions. Instructions available only in the 1LR2 are referred to as "level 2" instructions."
   
• The actual assembler SASM.EXE may be restricted to a specific level with the following command-line option:
  
  [SASM.DOC]
  P plevel Sets the processor level to "plevel" (0, 1, 2, or 3)
  
  [SASM.EXE -v?]
  -P codetype set processor (0=1LF2, 1=1LK7, 2=1LR2 [default=2])
  
  The exact same help message is returned by both version 1.56 from December 20, 1989 (as released with the first public version of the "HP-48 Software Development Tools"), and version 3.0.8 from June 12, 2002, corresponding to the latest version publicly available.
  
  And since we are in the fortunate position of having access to the latter’s source code, we only have to inspect a few files (especially opcodegen.c) to verify beyond any doubt that even at such a late stage, when all non-virtual Saturn CPU development had long ceased, level 2 instructions were still the most recent, while level 3 instructions were in fact never added. Not even Horror Mode (aka MASD syntax), introduced with the HP-49G in 1999, is considered level 3—which is only consistent since these are by no means actual instructions, but mere macros (which surely would have won haut la main the "International Obfuscated SASM Code Contest", if it existed).
  

It is therefore incorrect to claim that "more instructions" were added to the Clarke-Saturn, that "more instructions" were again added to the Yorke-Saturn, and not to mention that new instructions were indeed added to the Lewis-Saturn.


B.
If "level" is meant to refer to the different generations of the whole CPU architecture—including the bus and the chips attached to it—, then official HP literature counts four generations, as discussed in the article "An Advanced Scientific Graphing Calculator" by Diana K. Byrne, Charles M. Patton, David Arnett, Ted W. Beers, and Paul J. McClellan, in: Hewlett-Packard Journal, Vol. 45 no. 4, August 1994, pp. 6-22:

 
1. FIRST GENERATION: 1LF2 Saturn & 1LK7 Saturn
   
   "In the early days of the architecture (HP-71 to HP-28C), the CPU bus lines were actually routed around the circuit board and any RAM, ROM, or memory mapped I/O that was attached to the bus had to be custom-made with the bus interface attached. This had the advantage of allowing an arbitrary number of parts to be added to the system with assurance that the system would be capable of handling all of them in one way or another. It had the grave disadvantage of putting a price premium on such essential items as ROM and RAM." (p. 8)
   
   "In the standard [meaning: first-generation] device implementations, the size of the device (that is, the address space occupied by the device) is designed into the device." (p. 8)
   
    
2. SECOND GENERATION: 1LR2 Lewis
   
   "In the second-generation CPU chip, a fixed number of memory controllers were included onboard the CPU. The CPU bus was then, for all practical purposes, completely hidden within the CPU itself. The combination of external standard RAM or ROM together with one of the internal memory controllers was then equivalent (so far as the CPU bus is concerned) to a standard [meaning: first-generation] bus device." (p. 8)
   
   "In the second-generation chip, the size of the controllers was mask programmed at the time of manufacture since we knew exactly what size each controlled device would be." (p. 8)
   
    
3. THIRD GENERATION: 1LT8 Clarke
   
   "With the advent of plug-ins for the HP-48S/SX, the configuration capabilities of the memory controllers had to be expanded to include varying the apparent size of the memory controller to conform with the device being plugged in. This is one of the many advanced features in the third-generation, HP-48S/SX implementation of the architecture. This resizing feature, in addition to allowing plug-ins of various sizes, also presented the opportunity to explore expanded address modes, which we have come to call the "covered" technology." (p. 8)
   
   "The third-generation CPU chip has six memory controllers. In the HP-48SX, these are allocated to memory mapped I/O, system RAM, port 1, port 2, and system ROM, and there is one extra controller." (p. 8)
   
    
4. FOURTH GENERATION: Yorke (00048-80063)
   
   "The heart of the HP-48G/GX is a fourth-generation CPU chip. This custom ASIC is built around the original HP-71 processor [...]. This chip has four advantages over the third-generation chip used in the HP-48S/SX. First, it is produced using a different CMOS process, allowing better stability with onboard voltage regulation circuitry. Second, these improved voltage characteristics and several low-level optimizations allow the new CPU to operate at twice the speed of its predecessor. This speed increase gives it a 4-MHz bus rate. Third, the new CPU is packaged in a 160-pin quad flatpack, improving the manufacturability of the HP-48G/GX. Fourth, with all these improvements, the final cost is lower, increasing the budget for other hardware improvements to the calculator." (pp. 11-12)
   
   "While the HP-48G/GX has CPU functionally equivalent to the third-generation CPU [...] and thus has six memory controllers, these controllers are configured and used differently. [...] The controller previously allocated to port 2 is now used as a bank switch control, and the extra controller is now allocated to port 2. Furthermore, there are now as many as 34 layers over the last 128K bytes of address space." (p. 10)
   

C.
If "level" is meant to refer to a specific version of the CPU core, then the official term is "variation" or "version", as can be seen from the SASM.DOC passage quoted above. Of these we may legitimately count at least five (or six), if we only consider the non-virtual flagships:

 
1. 1LF2 or Saturn I
    
2. 1LK7 or Saturn II
    
3. 1LR2 Lewis IC containing Saturn III
    
4. 1LT8 Clarke IC containing Saturn IV
    
5. Yorke IC containing Saturn V
    
6. ( The New Yorke prototype may be added as containing Saturn VI. )
   

As for the Saturn CPUs included in the 1LR3 Sacajawea IC (used in mid-range Pioneers) and in the 1LU7 Bert IC (used in low-end Pioneers), they are best considered as sub-varieties of the one included in the Lewis IC (used in high-end Pioneers and second-generation Clamshells).

This way of counting might be at the origin of the unverified Wikipedia claim that the Yorke IC is "sometimes also known as Saturn 5 platform". (Where? By whom? When?)

In short:

                    +-------------+------------------+--------------+
                    | INSTRUCTION | CPU ARCHITECTURE |  SATURN CPU  |
                    |    LEVEL    |    GENERATION    | CORE VARIETY |
+-------------------+-------------+------------------+--------------+
| 1LF2 Saturn CPU   |      0      |      First       |     I        |
| 1LK7 Saturn CPU   |      1      |      First       |     II       |
| 1LR2 Lewis IC     |      2      |      Second      |     IIIa     |
| 1LR3 Sacajawea IC |      2      |    ( Second )    |     IIIb     |
| 1LU7 Bert IC      |      2      |    ( Second )    |     IIIc     |
| 1LT8 Clarke IC    |      2      |      Third       |     IV       |
|      Yorke IC     |      2      |      Fourth      |     V        |
+-------------------+-------------+------------------+--------------+

Unfortunately, the "levels" indicated in the Wikipedia article do not correspond to any of these commonly acknowledged uses.

Furthermore:

It is probably incorrect to refer to the Sacajawea IC with a hypothetical alternative part number 1LE2, but I have no official source to support that.

It is certainly incorrect to refer to the Lewis IC with part number 1LT8, see: Preston D. Brown, "HP-48SX Custom Integrated Circuit" in: Hewlett-Packard Journal, Vol. 42 no. 3, June 1991, p. 30:

"The HP 1LT8 IC is the single custom chip in the HP-48SX calculator."

The single source of all these errors seems to be the "names" page within Craig Finseth’s otherwise excellent "HPDATAbase". It really should be updated.

[EdS2]

Great info Giuseppe, thanks for posting it here!

[Jonathan Busby]

(06-27-2020 02:29 AM)Giuseppe Donnini Wrote:  The mere thought of using Wikipedia as a reliable source for information on the Saturn CPU hadn’t even begun to speculate about the merest possibility of crossing my mind...
But given the high expertise of its main author, I took the time to read the entire article, and would like to address a couple of issues:

If you are referring to "Jdbtwo", then that's me The issues that you found are not present in any content that I added -- there is another main author whose content I've mostly not touched as I'm afraid of "stepping on toes" I do plan on re-working the article though

Quote:In the chapter "Chipsets and applications" the different Saturn incarnations are classified according to their so-called "level", but it remains entirely unclear what is actually meant.

I presume that the "level" comes from the "level" referred to in the HP Tools SASM.DOC file :

Code:

Instructions available in all
Saturn CPUs are referred to as "level 0" instructions.
Instructions available in the 1LK7 and 1LR2 but not the 1LF2
are referred to as "level 1" instructions.  Instructions
available only in the 1LR2 are referred to as "level 2"
instructions.

Quote:A.
In original HP publications, the term "level" is used exclusively to refer to the set of instructions available for a given CPU. In that sense, there are exactly three levels:

1. Level 0 referring to the instruction set of the original stand-alone Saturn CPU (1LF2).
2. Level 1 referring to the instruction set of the redesigned, and improved, stand-alone Saturn CPU (1LK7).
3. Level 2 referring to the instruction set of the further improved Saturn CPU as it first appeared in the Lewis IC (1LR2).
   

And that’s all. Later (non-virtual) Saturn processors, i.e. those built into the Sacajawea IC (1LR3), the Bert IC (1LU7), the Clarke IC (1LT8), and the Yorke IC (00048-80063) all use the same level 2 instruction set.

Here are some official HP sources corroborating this point:

• SASM.DOC, p. 15 (reflecting the 1LR2 state of development, despite having been officially distributed for the first time with the "HP-48 Software Development Tools"):
  
  "The Saturn CPU has three variations used in several products. The 1LF2 was used in the first versions of the HP-71B. The 1LK7 is a variation of the 1LF2 used in later versions of the HP-71B, the HP-18C, and the HP-28C. The 1LR2 is an integrated CPU/ROM/RAM/Display Driver IC. Each new version of the Saturn CPU added new instructions to the Saturn instruction set. Instructions available in all Saturn CPUs are referred to as "level 0" instructions. Instructions available in the 1LK7 and 1LR2 but not the 1LF2 are referred to as "level 1" instructions. Instructions available only in the 1LR2 are referred to as "level 2" instructions."
• The actual assembler SASM.EXE may be restricted to a specific level with the following command-line option:
  
  [SASM.DOC]
  P plevel Sets the processor level to "plevel" (0, 1, 2, or 3)
  
  [SASM.EXE -v?]
  -P codetype set processor (0=1LF2, 1=1LK7, 2=1LR2 [default=2])
  
  The exact same help message is returned by both version 1.56 from December, 20th 1989 (as released with the first public version of the "HP-48 Software Development Tools") and version 3.0.8 from June, 12th 2002, corresponding to the latest version publicly available.
  
  And since we are in the fortunate position of having access to the latter’s source code, we only have to inspect a few files (especially opcodegen.c) to verify beyond any doubt that even at such a late stage, when all non-virtual Saturn CPU development had long ceased, level 2 instructions were still the most recent, while level 3 instructions were in fact never added. Not even Horror Mode (aka MASD syntax), introduced with the HP-49G in 1999, is considered level 3—which is only consistent since these are by no means actual instructions, but mere macros (which surely would have won haut la main the "International Obfuscated SASM Code Contest", if it existed).
  

It is therefore incorrect to claim that "more instructions" were added to the Clarke-Saturn, that "more instructions" were again added to the Yorke-Saturn, and not to mention that new instructions were indeed added to the Lewis-Saturn.

I was not the person who added the above problematic content to the Wikipedia article I'm planning on re-working the article in draft form in the next few days and then asking the other main editors if it's OK to proceed with publishing the re-work.

Quote:B.
If "level" is meant to refer to the different generations of the whole CPU architecture—including the bus and the chips attached to it—, then official HP literature counts four generations, as discussed in the article "An Advanced Scientific Graphing Calculator" by Diana K. Byrne, Charles M. Patton, David Arnett, Ted W. Beers, and Paul J. McClellan, in: Hewlett-Packard Journal, Vol. 45 no. 4, August 1994, pp. 6-22:

1. FIRST GENERATION: 1LF2 Saturn & 1LK7 Saturn
   
   "In the early days of the architecture (HP-71 to HP-28C), the CPU bus lines were actually routed around the circuit board and any RAM, ROM, or memory mapped I/O that was attached to the bus had to be custom-made with the bus interface attached. This had the advantage of allowing an arbitrary number of parts to be added to the system with assurance that the system would be capable of handling all of them in one way or another. It had the grave disadvantage of putting a price premium on such essential items as ROM and RAM." (p. 8)
   
   "In the standard [meaning: first-generation] device implementations, the size of the device (that is, the address space occupied by the device) is designed into the device." (p. 8)
2. SECOND GENERATION: 1LR2 Lewis
   
   "In the second-generation CPU chip, a fixed number of memory controllers were included onboard the CPU. The CPU bus was then, for all practical purposes, completely hidden within the CPU itself. The combination of external standard RAM or ROM together with one of the internal memory controllers was then equivalent (so far as the CPU bus is concerned) to a standard bus device." (p. 8)
   
   "In the second-generation chip, the size of the controllers was mask programmed at the time of manufacture since we knew exactly what size each controlled device would be." (p. 8)
3. THIRD GENERATION: 1LT8 Clarke
   
   "With the advent of plug-ins for the HP-48S/SX, the configuration capabilities of the memory controllers had to be expanded to include varying the apparent size of the memory controller to conform with the device being plugged in. This is one of the many advanced features in the third-generation, HP-48S/SX implementation of the architecture. This resizing feature, in addition to allowing plug-ins of various sizes, also presented the opportunity to explore expanded address modes, which we have come to call the "covered" technology." (p. 8)
   
   "The third-generation CPU chip has six memory controllers. In the HP-48SX, these are allocated to memory mapped I/O, system RAM, port 1, port 2, and system ROM, and there is one extra controller." (p. 8)
4. FOURTH GENERATION: Yorke (00048-80063)
   
   "The heart of the HP-48G/GX is a fourth-generation CPU chip. This custom ASIC is built around the original HP-71 processor [...]. This chip has four advantages over the third-generation chip used in the HP-48S/SX. First, it is produced using a different CMOS process, allowing better stability with onboard voltage regulation circuitry. Second, these improved voltage characteristics and several low-level optimizations allow the new CPU to operate at twice the speed of its predecessor. This speed increase gives it a 4-MHz bus rate. Third, the new CPU is packaged in a 160-pin quad flatpack, improving the manufacturability of the HP-48G/GX. Fourth, with all these improvements, the final cost is lower, increasing the budget for other hardware improvements to the calculator." (pp. 11-12)
   
   "While the HP-48G/GX has CPU functionally equivalent to the third-generation CPU [...] and thus has six memory controllers, these controllers are configured and used differently. [...] The controller previously allocated to port 2 is now used as a bank switch control, and the extra controller is now allocated to port 2. Furthermore, there are now as many as 34 layers over the last 128K bytes of address space." (p. 10)
   

Looks like the journal article may have included a typo in "This speed increase gives it a 4-MHz bus rate." -- This is incorrect : The bus/strobe rate of the Yorke SoC's internal Saturn bus and memory controllers is only ~2MHz, but the embedded Saturn CPU operates at ~4MHz. I remember Dave Arnett explaining the design being similar to a "486DX2" ( in terms of the clocking scheme ), but I can't seem to find the exact post on Google Groups.

( Note that in the following quote, the "code" tags were added by me to enclose the nice ASCII table as it wasn't being rendered correctly in Firefox ( On my Linux Mint 19.2 system at least ). )

Quote:C.
If "level" is meant to refer to a specific version of the CPU core, then the official term is "variation" or "version", as can be seen from the SASM.DOC passage quoted above. Of these we may legitimately count at least five (or six), if we only consider the non-virtual flagships:

1. 1LF2 or Saturn I
2. 1LK7 or Saturn II
3. 1LR2 Lewis IC containing Saturn III
4. 1LT8 Clarke IC containing Saturn IV
5. Yorke IC containing Saturn V
6. ( The New Yorke prototype may be added as containing Saturn VI. )
   

As for the Saturn CPUs included in the 1LR3 Sacajawea IC (used in mid-range Pioneers) and in the 1LU7 Bert IC (used in low-end Pioneers), they are best considered as sub-varieties of the one included in the Lewis IC (used in high-end Pioneers and second-generation Clamshells).

This way of counting might be at the origin of the unverified Wikipedia claim that the Yorke IC is "sometimes also known as Saturn 5 platform". (Where? By whom? When?)

In short:

Code:

                    +-------------+------------------+--------------+
                    | INSTRUCTION | CPU ARCHITECTURE |  SATURN CPU  |
                    |    LEVEL    |    GENERATION    | CORE VARIETY |
+-------------------+-------------+------------------+--------------+
| 1LF2 Saturn CPU   |      0      |      First       |     I        |
| 1LK7 Saturn CPU   |      1      |      First       |     II       |
| 1LR2 Lewis IC     |      2      |      Second      |     IIIa     |
| 1LR3 Sacajawea IC |      2      |    ( Second )    |     IIIb     |
| 1LU7 Bert IC      |      2      |    ( Second )    |     IIIc     |
| 1LT8 Clarke IC    |      2      |      Third       |     IV       |
|      Yorke IC     |      2      |      Fourth      |     V        |
+-------------------+-------------+------------------+--------------+

Unfortunately, the "levels" indicated in the Wikipedia article do not correspond to any of these commonly acknowledged uses.

Furthermore:

It is probably incorrect to refer to the Sacajawea IC with a hypothetical alternative part number 1LE2, but I have no official source to support that.

It is certainly incorrect to refer to the Lewis IC with part number 1LT8, see: Preston D. Brown, "HP-48SX Custom Integrated Circuit" in: Hewlett-Packard Journal, Vol. 42 no. 3, June 1991, p. 30:

"The HP 1LT8 IC is the single custom chip in the HP-48SX calculator."

The single source of all these errors seems to be the "names" page within Craig Finseth’s otherwise excellent "HPDATAbase". It really should be updated.

I agree that most of the above errors seem to stem from inaccuracies in Craig Finseth's database.

At any rate, thanks for all the excellent info and corrections! I'll be sure to include them in the article re-work.

Regards,

Jonathan

[Raymond Del Tondo]

(06-27-2020 02:29 AM)Giuseppe Donnini Wrote:  Not even Horror Mode (aka MASD syntax), introduced with the HP-49G in 1999, is considered level 3—which is only consistent since these are by no means actual instructions, but mere macros (which surely would have won haut la main the "International Obfuscated SASM Code Contest", if it existed).

You nailed it:-)

[Giuseppe Donnini]

I confess, indeed, that I mistook you for the main author of that article, Jonathan, and I’m glad to see that you took it lightly. Please accept my apologies!

According to my own database on the subject, the i486DX2-comparison you refer to was not drawn by Dave Arnett, but by Preston Brown. The reason you couldn’t find the exact post on Google Groups is that it is simply not there anymore! It’s part of that ill-fated comp.sys.hp48-period, running from spring 1993 to spring 1994, that seems to have been devoured by some mysterious Chronophagos. But a snippet of it has been preserved on Joe Horn’s Goodies Disk #9 under the name "SPEEDUP.DOC" (in the "POSTINGS" sub-directory), a copy of which can also be found here.

Thanks for your outstanding contributions in general, Jonathan! I'm really looking forward to your reworking of the article!