(HP71B) RAM access in HP71B; how it works?

[floppy]

Hello,
I would like to understand how RAM is accessed in HP71B.
a) in the port of the card reader place
b) in the front ports

For this, I need few feedbacks from the community.
Depending of the gathered knowledge, I will update this post.
Except somebody has already an extensive documentation for RAM interaction or RAM emulation (probably already done at FRAM71B) and reading it would bring all answer
(now, I am reading the HW and SW IDS, Multimod PIC codes thanks to Mark Fleming,.. unfortunately FRAM71 stay closed like a mollusc shell).

So far I understood (please correct me if wrong).
a) Access of Card Reader RAM is similar to front port RAM for accessing RAM from the OS and its Bus
b) maximum 4*32KB RAM can be accessed in one Port
c) each RAM Module can have 1 to 4 RAM chips with their own local control chip (if hardware)
d) at power on, the HP71B look all ports, then depending of the feedbacks from the RAM control chips, it store the informations on his own in an area in order to remember it at next power on; a RAM map is then created by the OS
e) the RAM module dont store any data in it for own configuration; the HP71B OS store only in an own area

So far not seen:
- bus command for processing a new RAM configuration
- 1LJ4 chip = apparently a RAM control chip: was a reverse engineering done for understanding how it works?
- differences in command for addressing 1 to 4* 32KB RAMs
- how an 1LJ4 chip recognize this is the first ON (cold start) or this is a ON after a cold start

You see, a lot of questions. I will do my best to write the summary here. Except all is known, then I will delete that post (after receiving data with several informations).

[KeithB]

HP already did:
https://literature.hpcalc.org/community/...rdware.pdf

[mfleming]

(04-09-2024 05:31 PM)KeithB Wrote:  HP already did:
https://literature.hpcalc.org/community/...rdware.pdf

Well yes, it's all there . . . but that's like saying the picture on the front of a jigsaw puzzle box is "all there" inside the box - once you put all the pieces in their proper place

There is quite a bit to learn how devices work in the 71B, most but not all of it explained in the IDS. I'll give you a high-level handwaving idea for a starting point. You can dig in from there.

• When the 71B wakes up, it probes each port in turn by raising and later lowering the port's individual Daisy In signal. This configuration process is done twice, first to identify what is in each port, and a second time to provide valid addresses for all devices in each port.
• The 71B then sends out an ID command. The device receiving the Daisy In signal will respond with a five nibble identification string that specifies what it is, how big it is, etc. If there is no response to the ID command then the port is empty or the end of a chain of devices has been reached.
• Once receiving a valid response, the 71B will send a CONFIG command with a five nibble address for the chip. On the first discovery pass, all devices are given the $40000 address. In the second configuration pass each device is placed in the address space (32KB and larger devices from the top down, smaller from the bottom up).
• If there are multiple devices in a given port then devices are daisy chained together, where each responding device passes the Daisy In signal to the next device in the chain once it has been given a configuration address.
  

Note that in the first discovery pass an extra ID command goes out, and a lack of response terminates the discovery phase for that port. Afterwards, the Daisy In signal for that port is lowered as the 71B goes to the next port.

In the second configuration phase, for a non-empty port the Daisy In signal is raised but no ID command is needed since the 71B knows what devices are in the port. A series of CONFIG commands are sent to put each device in their proper place in the address space.

J-F, please be sure to razz me for anything wrong I have wrong

~Mark

[KeithB]

"but that's like saying the picture on the front of a jigsaw puzzle box is "all there" inside the box - once you put all the pieces in their proper place"

Yeah, I am cranky today, so I got snarky.

I also missed that Floppy said he was already referring to the IDS.

[brouhaha]

(04-09-2024 05:26 PM)floppy Wrote:  a) Access of Card Reader RAM is similar to front port RAM for accessing RAM from the OS and its Bus

Yes, the card reader and HP-IL ports are basically just funny-shaped ports. The card reader port pinout doesn't include daisy-chain out, so it's not possible to wire more than one physical module to it. Port 1 and the card reader port have the OD (output disable) signal, necessary if one wants to replace the mainframe ROM. There are a few other minor variations in how the ports are wired, but they don't matter for normal ROM or RAM.

Quote:b) maximum 4*32KB RAM can be accessed in one Port
c) each RAM Module can have 1 to 4 RAM chips with their own local control chip (if hardware)

Those aren't the limits.

HP RAM modules don't have a "local control chip". HP's RAM chips connect to the Saturn bus directly.

The 1LJ4 was, AFAIK, not used in any HP product. They made it available to some OEMs, and it may have served as a prototype for the industry-standard memory interface incorporated in the later Lewis, Clarke, and Yorke SoCs.

The actual HP-71B limits are:
* a port can contain up to 15 modules
* a module can contain up to 15 sequences
* a sequence can contain up to 15 chips of the same type and size
* a RAM or ROM chip can be up to 32 KiB
* maximum size of the system buffer area which stores the configuration
* maximum total address space of 512 KiB, of which 64 KiB is mainframe ROM, and 32 KiB is reserved for I/O.

HP ROM chips were 16 KiB, and HP RAM chips were 1 KiB, but those were just the sizes chosen for cost-effective manufacturing using HP's then-current CMOS technology. The architecture developers anticipated that larger memory sizes would appear in the future, though HP didn't make them.

You'll hit the configuration buffer size limit, and more likely, the address space limit, before you get anywhere close to the maximum number of possible chips. The HP-71B configuration code will put any extra chips it can't find address space for into a "garbage dump" at the end of the address space, then unconfigure them. RAM chips will still retain their contents, as long as power is applied, so if IRAM (port-addressed indpendent RAM) ends up in the garbage dump, a later change to the machine configuration may make them available again without loss of data.

The need for the garbage dump area appears to render the end of the address space unusable. How much is "the end" depends on the size of the largest memory chip that has to be put into the garbage dump.

Quote:- 1LJ4 chip = apparently a RAM control chip: was a reverse engineering done for understanding how it works?

How it works is by translating between Saturn bus and industry-standard byte-wide memory (RAM and EPROM). I once saw an HP specification fo rthe 1LJ4, but unfortunately do not have a copy. The specification didn't really give any details of "how it works". You hook up a Saturn bus to it, and some byte-wide memory chips, and set a few pins to configure the chip types and sizes, and then it just works. While the Saturn bus is more complicated than the byte-wide memory the 1LJ4 connect to, it's not so complicated that a digital designer couldn't come up with an equivalent, and of course that has been done several times.

Quote:- differences in command for addressing 1 to 4* 32KB RAMs

The differences in addressing various numbers of RAM chips, and various sizes, is all partof the configuration process. The chips wire up identically to the Saturn bus. There is no electrical difference in the addressing. The configuration process reads the identity of each (unconfigured) chip, which includes its type and size, then tells it what address to use.

Quote:- how an 1LJ4 chip recognize this is the first ON (cold start) or this is a ON after a cold start

It doesn't. THe 1LJ4 is powered from the HP-71B power (battery or AC adapter), regardless of whether the HP-71B is "ON" or "OFF". Functionally, it behaves the same as "normal" Saturn RAM and ROM; it doesn't do anything special at electrical power-up other than clear its configuration flip-flop just like the normal Saturn memories. It doesn't need to know about the HP-71B "ON" or "OFF" state as seen by the user.