The mere thought of using Wikipedia as a reliable source for information on the Saturn CPU hadn’t even begun to speculate about the merest possibility of crossing my mind...
But given the high expertise of its main author, I took the time to read the entire article, and would like to address a couple of issues:
In the chapter "Chipsets and applications" the different Saturn incarnations are classified according to their so-called "level", but it remains entirely unclear what is actually meant.
A.
In original HP publications, the term "level" is used exclusively to refer to the set of instructions available for a given CPU. In that sense, there are exactly three levels:
- Level 0 referring to the instruction set of the original stand-alone Saturn CPU (1LF2).
- Level 1 referring to the instruction set of the redesigned, and improved, stand-alone Saturn CPU (1LK7).
- Level 2 referring to the instruction set of the further improved Saturn CPU as it first appeared in the Lewis IC (1LR2).
And that’s all. Later (non-virtual) Saturn processors, i.e. those built into the Sacajawea IC (1LR3), the Bert IC (1LU7), the Clarke IC (1LT8), and the Yorke IC (00048-80063) all use the same level 2 instruction set.
Here are some official HP sources corroborating this point:
- SASM.DOC, p. 15 (reflecting the 1LR2 state of development, despite having been officially distributed for the first time with the "HP-48 Software Development Tools"):
"The Saturn CPU has three variations used in several products. The 1LF2 was used in the first versions of the HP-71B. The 1LK7 is a variation of the 1LF2 used in later versions of the HP-71B, the HP-18C, and the HP-28C. The 1LR2 is an integrated CPU/ROM/RAM/Display Driver IC. Each new version of the Saturn CPU added new instructions to the Saturn instruction set. Instructions available in all Saturn CPUs are referred to as "level 0" instructions. Instructions available in the 1LK7 and 1LR2 but not the 1LF2 are referred to as "level 1" instructions. Instructions available only in the 1LR2 are referred to as "level 2" instructions."
- The actual assembler SASM.EXE may be restricted to a specific level with the following command-line option:
[SASM.DOC]
P plevel Sets the processor level to "plevel" (0, 1, 2, or 3)
[SASM.EXE -v?]
-P codetype set processor (0=1LF2, 1=1LK7, 2=1LR2 [default=2])
The exact same help message is returned by both version 1.56 from December 20, 1989 (as released with the first public version of the "HP-48 Software Development Tools"), and version 3.0.8 from June 12, 2002, corresponding to the latest version publicly available.
And since we are in the fortunate position of having access to the latter’s source code, we only have to inspect a few files (especially opcodegen.c) to verify beyond any doubt that even at such a late stage, when all non-virtual Saturn CPU development had long ceased, level 2 instructions were still the most recent, while level 3 instructions were in fact never added. Not even Horror Mode (aka MASD syntax), introduced with the HP-49G in 1999, is considered level 3—which is only consistent since these are by no means actual instructions, but mere macros (which surely would have won haut la main the "International Obfuscated SASM Code Contest", if it existed).
It is therefore incorrect to claim that "more instructions" were added to the Clarke-Saturn, that "more instructions" were again added to the Yorke-Saturn, and not to mention that new instructions were indeed added to the Lewis-Saturn.
B.
If "level" is meant to refer to the different generations of the whole CPU architecture—including the bus and the chips attached to it—, then official HP literature counts four generations, as discussed in the article "An Advanced Scientific Graphing Calculator" by Diana K. Byrne, Charles M. Patton, David Arnett, Ted W. Beers, and Paul J. McClellan, in:
Hewlett-Packard Journal, Vol. 45 no. 4, August 1994, pp. 6-22:
- FIRST GENERATION: 1LF2 Saturn & 1LK7 Saturn
"In the early days of the architecture (HP-71 to HP-28C), the CPU bus lines were actually routed around the circuit board and any RAM, ROM, or memory mapped I/O that was attached to the bus had to be custom-made with the bus interface attached. This had the advantage of allowing an arbitrary number of parts to be added to the system with assurance that the system would be capable of handling all of them in one way or another. It had the grave disadvantage of putting a price premium on such essential items as ROM and RAM." (p. 8)
"In the standard [meaning: first-generation] device implementations, the size of the device (that is, the address space occupied by the device) is designed into the device." (p. 8)
- SECOND GENERATION: 1LR2 Lewis
"In the second-generation CPU chip, a fixed number of memory controllers were included onboard the CPU. The CPU bus was then, for all practical purposes, completely hidden within the CPU itself. The combination of external standard RAM or ROM together with one of the internal memory controllers was then equivalent (so far as the CPU bus is concerned) to a standard [meaning: first-generation] bus device." (p. 8)
"In the second-generation chip, the size of the controllers was mask programmed at the time of manufacture since we knew exactly what size each controlled device would be." (p. 8)
- THIRD GENERATION: 1LT8 Clarke
"With the advent of plug-ins for the HP-48S/SX, the configuration capabilities of the memory controllers had to be expanded to include varying the apparent size of the memory controller to conform with the device being plugged in. This is one of the many advanced features in the third-generation, HP-48S/SX implementation of the architecture. This resizing feature, in addition to allowing plug-ins of various sizes, also presented the opportunity to explore expanded address modes, which we have come to call the "covered" technology." (p. 8)
"The third-generation CPU chip has six memory controllers. In the HP-48SX, these are allocated to memory mapped I/O, system RAM, port 1, port 2, and system ROM, and there is one extra controller." (p. 8)
- FOURTH GENERATION: Yorke (00048-80063)
"The heart of the HP-48G/GX is a fourth-generation CPU chip. This custom ASIC is built around the original HP-71 processor [...]. This chip has four advantages over the third-generation chip used in the HP-48S/SX. First, it is produced using a different CMOS process, allowing better stability with onboard voltage regulation circuitry. Second, these improved voltage characteristics and several low-level optimizations allow the new CPU to operate at twice the speed of its predecessor. This speed increase gives it a 4-MHz bus rate. Third, the new CPU is packaged in a 160-pin quad flatpack, improving the manufacturability of the HP-48G/GX. Fourth, with all these improvements, the final cost is lower, increasing the budget for other hardware improvements to the calculator." (pp. 11-12)
"While the HP-48G/GX has CPU functionally equivalent to the third-generation CPU [...] and thus has six memory controllers, these controllers are configured and used differently. [...] The controller previously allocated to port 2 is now used as a bank switch control, and the extra controller is now allocated to port 2. Furthermore, there are now as many as 34 layers over the last 128K bytes of address space." (p. 10)
C.
If "level" is meant to refer to a specific version of the CPU core, then the official term is "variation" or "version", as can be seen from the SASM.DOC passage quoted above. Of these we may legitimately count at least five (or six), if we only consider the non-virtual flagships:
- 1LF2 or Saturn I
- 1LK7 or Saturn II
- 1LR2 Lewis IC containing Saturn III
- 1LT8 Clarke IC containing Saturn IV
- Yorke IC containing Saturn V
- ( The New Yorke prototype may be added as containing Saturn VI. )
As for the Saturn CPUs included in the 1LR3 Sacajawea IC (used in mid-range Pioneers) and in the 1LU7 Bert IC (used in low-end Pioneers), they are best considered as sub-varieties of the one included in the Lewis IC (used in high-end Pioneers and second-generation Clamshells).
This way of counting might be at the origin of the unverified Wikipedia claim that the Yorke IC is "sometimes also known as Saturn 5 platform". (Where? By whom? When?)
In short:
+-------------+------------------+--------------+
| INSTRUCTION | CPU ARCHITECTURE | SATURN CPU |
| LEVEL | GENERATION | CORE VARIETY |
+-------------------+-------------+------------------+--------------+
| 1LF2 Saturn CPU | 0 | First | I |
| 1LK7 Saturn CPU | 1 | First | II |
| 1LR2 Lewis IC | 2 | Second | IIIa |
| 1LR3 Sacajawea IC | 2 | ( Second ) | IIIb |
| 1LU7 Bert IC | 2 | ( Second ) | IIIc |
| 1LT8 Clarke IC | 2 | Third | IV |
| Yorke IC | 2 | Fourth | V |
+-------------------+-------------+------------------+--------------+
Unfortunately, the "levels" indicated in the Wikipedia article do not correspond to any of these commonly acknowledged uses.
Furthermore:
It is probably incorrect to refer to the Sacajawea IC with a hypothetical alternative part number 1LE2, but I have no official source to support that.
It is certainly incorrect to refer to the Lewis IC with part number 1LT8, see: Preston D. Brown, "HP-48SX Custom Integrated Circuit" in:
Hewlett-Packard Journal, Vol. 42 no. 3, June 1991, p. 30:
"The HP 1LT8 IC is the single custom chip in the HP-48SX calculator."
The single source of all these errors seems to be the
"names" page within Craig Finseth’s otherwise excellent "HPDATAbase". It really should be updated.
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