New Yorke chip in hardware

[Jonathan Busby]

(07-16-2020 08:02 AM)EdS2 Wrote:  Two disadvantages for me: only available in BGA packages, and not 5V tolerant. These are of course minor points, especially for a new standalone calculator-type of application.

Well, this can be easily gotten around by using a small daughterboard and a μC voltage regulator and supervisory IC. The power supplies in eg. the HP48G series and HP48S series and older HP calculators are not only ancient, but not that efficient compared to a modern tiny voltage regulator chip.

Quote:An advantage (for me) of Lattice's ICE40 range, hopefully including these low power ones: an open source toolchain is available.

Unfortunately ( for me ), said toolchain doesn't yet support the Lattice iCE40 Ultra and UltraLite FPGAs, which I've been using -- I have to use Aldec's proprietary Active-HDL simulator for timing simulation and post place-and-route-simulation and Lattice's proprietary iCEcube2 EDA tool for synthesis, place-and-route, bitstream generation and device programming Also, the Active-HDL version that is packaged with Lattice's iCEcube2 EDA software is crippled with respect to its performance and some language features such as UVM SystemC and SystemVerilog and it's only 32-bit and only runs on Windows -- if you want the uncrippled version, you have to pay $2K USD per year . I usually use Verilator though for pre-synthesis simulation of the synthesizeable constructs of SystemVerilog and Verilog-2001. Verilator is not only opensource but it's *much*, *much* faster than "Active-HDL". Still, I have to use Active-HDL for the timing and post place-and-route simulation.

Regards,

Jonathan