HP-71B MultiMod ROM Emulator User Manual

[mfleming]

One of the documentation "errors" that bit me was the timing information in the H/W IDS. It states that Tacc, "*STR low to data-out valid" (p. 9-4), is a maximum of 200 ns. Not so with the earliest Saturn chip, as confirmed by J-F with an oscilloscope. Seems the chips that are in early Titans were a bit slow to serve up data on the bus. The timing specs in the IDS were probably written with newer Saturns in mind.

At one point I tried sampling the bus early in the strobe cycle rather than at midpoint. My code worked fine with a newer 71B (2724A). On an older model (2406A) the data was not yet valid so the code usually, not always, saw a NOP. On the occasions when it saw something random: Bang. Crash. Battery pull.