FRAM71 : Configuration Spreadsheet [2021-01-31]

[Sylvain Cote]

Hello Hans,

First, thank you for your previous answers, very much appreciated.

While doing the final testing before releasing the spreadsheets with validation, I stumbled upon something unexpected or forgotten.
The following behavior has been there all along since the original FRAM71 and still is in FRAM71B.
When I try to create a virtual module with different module size, it creates something of a problems, see the following testing results ...

Code:

        |                        |                  |        | ---[ SHOW  PORT ]--- | --------[ MEMBUFF  OUTPUT ]-------- | 
Module  | Test                   | POKE "2C000",... | MEM(5) | Port   Size    Type  | Port  Dev  Seq  Size  Addr   Type   | Comment
------- | ---------------------- | ---------------- | ------ | ----  ------  ------ | ----  ---  ---  ----  -----  ------ | --------------------------------

Code:

FRAM71B | #01 → 96 = 32+32+32    | "13149500"       |  98299 |   5    98304  1:IRAM |   5    0    0    96   D0000  1:IRAM | Expected
FRAM71B | #02 → 48 = 16+16+16    | "2324A500"       |  49147 |   5    49152  1:IRAM |   5    0    0    48   48000  1:IRAM | Expected
------- | ---------------------- | ---------------- | ------ | ----  ------  ------ | ----  ---  ---  ----  -----  ------ | --------------------------------
FRAM71B | #03 → 80 = 32+32+16    | "1314A500"       |  65531 |   5    65536  1:IRAM |   5    0    0    64   E0000  1:IRAM | Unexpected
        |                        |                  |        |   5    16384  1:IRAM |   5    0    1    16   48000  1:IRAM | 
------- | ---------------------- | ---------------- | ------ | ----  ------  ------ | ----  ---  ---  ----  -----  ------ | --------------------------------
FRAM71B | #04 → 80 = 32+16+32    | "13249500"       |  32763 |   5    32768  1:IRAM |   5    0    0    32   E0000  1:IRAM | Unexpected
        |                        |                  |        |   5    16384  1:IRAM |   5    0    1    16   40000  1:IRAM | 
        |                        |                  |        |   5    32768  1:IRAM |   5    0    2    32   D0000  1:IRAM |

In tests #01 and #02:

• I have create a virtual port with three identical FRAM chip size
• the HP-71 only sees one virtual chip instead of the individual chips.
  

In tests #03 and #04:

• I have create a virtual port with two identical FRAM chip size and one different FRAM chip size
• depending on how those FRAM chips are mapped the HP-71 only sees two or three chips instead of a single virtual chip
• this creates an issue when these chips are mapped to the port number, they get the same port number.
  

If I expand my test #03

• MEM(5) // display 65531 that is the size of the combined two 32K chips
• CLAIM :PORT(5) // transfer the 64KB virtual chip from IRAM to MAIN RAM
• RUN MEMBUF shows
  
  Code:
  

  Port  Dev  Seq  Size  Addr   Type  
----  ---  ---  ----  -----  ------
  5    0    0     64  30000  0:MAIN
  5    0    1     16  68000  1:IRAM
• MEM(5) // display 16379 that is the size of the last 16K chip
• CLAIM :PORT(5) // transfer the 16KB virtual chip from IRAM to MAIN RAM
• RUN MEMBUF shows
  
  Code:
  

  Port  Dev  Seq  Size  Addr   Type  
----  ---  ---  ----  -----  ------
  5    0    0     64  30000  0:MAIN
  5    0    1     16  50000  0:MAIN
  if I go the reverse route by freeing port 5
• FREE :PORT(5) // transfer the 64KB virtual chip from MAIN to IRAM
• MEM(5) // display 65531 that is the size of the combined two 32K chips
• RUN MEMBUF shows
  
  Code:
  

  Port  Dev  Seq  Size  Addr   Type  
----  ---  ---  ----  -----  ------
  5    0    1     16  30000  0:MAIN
  5    0    0     64  E0000  1:IRAM
• FREE :PORT(5) // transfer the 16KB virtual chip from MAIN to IRAM
• MEM(5) // display 65531 that is the size of the combined two 32K chips
• RUN MEMBUF shows
  
  Code:
  

  Port  Dev  Seq  Size  Addr   Type  
----  ---  ---  ----  -----  ------
  5    0    0     64  E0000  1:IRAM
  5    0    1     16  48000  1:IRAM

What I find strange here is that we have two different behavior, one for identical chip size and one for different chip size.
Also the second one introduce an issue from the 71B OS perspective, multiple port with the same number.

Sylvain

PS: Testing has been done with a FRAM71 (2015 production) and with a FRAM71B (2021 production)

PPS: for the FRAM71/FRAM71B newbies here, this is an edge case and should not derail you from using this great module.

edit 1 : typos
edit 2 : PPS added