A TTL approach to the HP-35

[Alejandro Paz(Germany)]

I have been working on and off for the last days and more or less I have an idea how the alu & the registers should work and look like, even if I haven't finalized it yet.
The central questions are how is the program going to be stored and executed ? which opcodes does the processor understands ?, for me just one question.

The original 10 bit opcodes are too compact, I think they need too much logic to be decoded, think about the field storage for example, you need a kind of look up table. An expanded version where the source, destination and field start and end are explicitly stored sounds cheaper in logic terms to me, just route these signals to the respective registers, counters. An opcode then would be a series of enable signals plus the fields. I think that this is much more workable than the 10 bit compact form.

This only solves part of the problem. Opcodes like stack push, pop and rotate need extra sequencers, unless they are encoded as a series of opcodes, meaning the original program needs some tweaking besides opcode replacement. I haven't thought it through yet. I'm still concentrated on the alu/regs block and that it performs the basic register-register operations by itself.
The question remains, one could assign say 8 micro opcodes per 10 bit opcode, memory is cheap nowadays... as one German saying goes "Es gibt immer einen Hacken", something along the lines "nothing is free". Either I microcode the opcodes or I microcode the program. I think the second approach seems easier on logic.

My FPGA version decodes the 10 bit opcodes and has a big look up table and a sequencer or two, for decoding and controlling the data flow and a true dual port register file, this makes exchanges a breeze and the other operations too. One do not think on how many chips maybe needed for some feature. Feeding P into the field start or end is also a small concern becuase it needs another mux and a special treatment.