First step ...
To do the following steps you need:
Configuration steps ...
The following steps needs to be done when you need to connect/disconnect the serial cable to/from the 41CL.
Code:
[ON] // power off
// connect/disconnect serial cable to/from the 41CL and to/from the computer.
[ON] // power on
MMUEN // the MMU often disable itself when the connection/disconnection of the serial plug occur.
The following steps needs to be executed when you want to manually transfer a ROM with the serial port.
They also need to be done when the 41CL goes OFF automatically or when you get a OVERRUN message while transmitting.
Code:
[ON] // OVERRUN case only - power-cycling power off
[ON] // OVERRUN case only - power-cycling power on
50
PTURBO // turbo 50x is needed in order to have a successfull serial port transfer
SERINI // initialize serial port
48
PBAUD // setup the baud rate to 4800 baud
Transmission steps ...
We have these 4 ROMs to transfer.
Code:
Filename YCRC RAM Address
------------ ---------- -----------
LIBRARY4.ROM 0x0C534356 830000
WARPB1.ROM 0x1AB1C614 831000
WARPB2.ROM 0x73A2E747 832000
WARPB3.ROM 0xC89E6ADD 833000
834000 although there is no ROM at this address, it will be needed later
I will show the steps for LIBRARY4.ROM but you will have to repeat these steps for the other ROMs as well.
On the 41CL
Code:
"830000-0FFF" // RAM address where LIBRARY4.ROM will be loaded
[XEQ] [ALPHA] YIMP // YIMP command is left dangling
On the computer
Code:
java -jar clupdate-1.1.0.jar --upload LIBRARY4.ROM /dev/tty.usbserial 4800 [return]
You should get the following message
Code:
HH:MM:SS --upload [fileName: LIBRARY4.ROM] [portName: /dev/tty.usbserial] [baudRate: 4800]
HH:MM:SS File LIBRARY4.ROM loading ... done [YCRC=0x0C534356 Rev:2021-06-25]
HH:MM:SS Serial /dev/tty.usbserial opened.
HH:MM:SS Sleeping 5 seconds before starting file transfer
On the 41CL and within 5 seconds of the above message
Code:
[ALPHA] // execute YIMP command
"830" // RAM address where LIBRARY4.ROM is located
YCRC // request a CRC to validate if we got the complete ROM, I get 0C534356, perfect match, it is valid
MMU configuration steps ...
Code:
MMUDIS // disable MMU
MMUCLR // clear MMU configuration
"YFNX" // CL Extreme ROM
PLUG1U // page 9 = CL Extreme ROM
MMUEN // enable MMU
"-830 4" // page 4 = Library #4 in RAM address 830
PPLUG // activate page 4
"OSX3 8" // page 8 = OS/X
PPLUG // activate page 8
"PWRX A" // page A = PowerCL Extreme
PPLUG // activate page A
"834000-0000" // since the PPLUG command assume 4 pages bank switching we need to erase the fourth one
YMCLR // do the erasing
"*831 B" // page B = WARP Core with bank switched code located at RAM addresses 831, 832, 833 & 834
PPLUG // activate page B
"HEP3 C" // page C = HEPAX Plus
PPLUG // activate page C
"HEP2 D" // page D = HEPAX 4H
PPLUG // activate page D
"820000-0000" // 4K QROM at page 820 (will becomes HEPAX RAM at page E)
YMCLR // clear QROM content
"821000-0000" // 4K QROM at page 820 (will becomes HEPAX RAM at page F)
YMCLR // clear QROM content
"+820 E" // pages E = 820 & F = 821
PPLUG // activate pages E & F
HEPINI // Initialize HEPAX RAM
// at the first prompt, enter 2 (for 2 pages)
// then at the second prompt, enter E (the first HEPAX RAM page)
OFF // power cycle off
ON // power cycle on
HEPDIR // you should see H:DIR EMPTY and 1304 in X (free HEPAX DATA registers)
Have fun!
Sylvain