Casio 4bit SRAM replacement project

[Jeff_Birt]

It all started when I got a Casio PB-100 in very good shape but with a duff 2K SRAM chip. These are odd little beasts made by Hitachi for Casio that sit on the Casio 4bit bus, the same bus that goes to the expansion connector. These are unobtainium of course except for stealing one from another Casio that used the same chips.

I found that a nice guy in Poland had reverse engineered the bus protocol already which made my job much, much easier: http://pisi.com.pl/piotr433/hardware.htm . The PB-700 shown on his webpage is like a PB-100 with two 2K chips on board.

It is rather convenient that the same signals that go to the RAM also go to the expansion connector. This was the reason that I designed a compatible connector which I posted about a few weeks ago. Funny how projects seem to spin off side projects.

I was able to first capture the bus signals with a cheap Saleae Logic8 to have a look for myself. Then I set about trying to find a good microcontroller to use to simulate the SRAM chip. It had to be very low power, have more than 2K of RAM and enough I/O. I found that a PIC 16F18446 seemed like it would work, and there was an inexpensive dev board with built in programmer/debugger.

The choice of the PIC has been a stumbling block. I had not used one before and the architecture is defiantly different. The MPLAB X IDE is also a real PITA, very buggy, very bloated and a constant source of frustration. I have found that the peripherals built into this chip have come in really handy though and they can be switched off when not needed to save power. For example I was able to generate the quadrature clock the Casio bus uses with a combination of TMR+PWM+CWG.

This week figured out how to sync the data and control signals with this hardware generated clock (so same procedure can be used to sync output of PIC to clock generated by Casio.) I started with wanting to generate the clock myself to try and dump the RAM from the Casio as it seemed like good stepping stone. Luckily when in idle mode the Casio stops the clock and tristates the bus for long periods of time. Piotr from the website above had already figured this out and clued me into the idea.

There are two images attached. One is the 'real' output of the PB-100 and one is simulated by the PIC. It was exciting getting this to work this morning. You can see there is about 1.5us lag from the falling edge of CLK2 to the falling edge of /CE and /OP. Each 'bit time' seems to be two complete cycles of CLK1 so I'm guessing that it latches data in on the second falling edge of CLK1, i.e. the middle of the bit time. This short lag of 1.5us will not be an issue if this is the case.

I thought I would post now as sort of a way to keep a log of the project and maybe the ideas, even those that did not work will be of use to others.