Panasonic HHC ROM 'capules'

[brouhaha]

If you look at the schematics, and trace back the gates of the transistors that switch power to the capsule sockets, you'll see that the 6502 phase 2 clock is gated into them, so even if a capsule is selected on consecutive memory cycles, the supply to the capsule pulses.

There's another interesting wrinkle. If a CMOS memory device is used, whether it's an old 27Cnn EPROM, or a modern flash, FRAM, MRAM, etc., when the power supply on pin 24 of the socket is switched off, the device will partially power itself from any address and data lines that are in a logic 1 state, because the ESD protection diodes in the chip will be forward biased. This has both good and bad consequences for trying to make the memory device work reliably on the HHC, but in general it makes the analysis more difficult.