Panasonic HHC ROM 'capules'

[Jeff_Birt]

The phi0 clock is output by the custom ASIC chip. This chip has a config register with a bit that is set when accessing 'slow' memory. It looks like the effect is that phi0 is /8, i.e. 1.2mhx to 150khz. If so, this will provide a lot more time for the ROM to become stable.

The uses of the open collector invertors to short out VCC to the ROMs on deselection is also odd. Especially given that they all seem to have come with a cap tacked across VCC and VSS. I have another computer in pieces on my bench right now. When I'm done with it, I'll poke around on the HHC and see if I can see this /8 feature in action on the scope.

If nothing else, it is an interesting design...