Panasonic HHC ROM 'capules'

[brouhaha]

(01-16-2023 02:32 AM)Jeff_Birt Wrote:  The phi0 clock is output by the custom ASIC chip. This chip has a config register with a bit that is set when accessing 'slow' memory. It looks like the effect is that phi0 is /8, i.e. 1.2mhx to 150khz. If so, this will provide a lot more time for the ROM to become stable.

That still only gives a little over 3us from power application to data required to be valid, which is not enough for any of the modern memory chips to power up. If the new module either had a batter, or a supercap that got charged (through a diode from the capsule connector pin 24), maybe it would work. Some circuitry, maybe just a single CMOS gate, would be necessary to derive a chip select, basically by inverting the pin 24 level, so that the memory while powered by the battery/supercap without power from the computer would not be selected and try to drive the bus.

Given how big even "small" modern memory chips are, maybe a new capsule could have a half-pitch DIP switch (e.g. CTS 218) to select between multiple images. Or a fine-pitch header and jumper blocks. Though if it's easy to hook up a programming fixture, maybe it's unnecessary.