Panasonic HHC ROM 'capules'

[brouhaha]

So Reensas flash also can take 260 us from power up to first read, as with the other modern memory chips I looked at. That seems far to long even in the HHC slow mode.

it's a worst-case spec, but even if a typical part only needed half of that, it would still be far too long.

Previously Jeff wrote:

Quote:With a 1mhz clock on a 6502 one instruction cycle is 1us. Each opcode takes 2-6 instruction cycles so it would take 17~50 opcodes to eat up the 100us power rise time of the flash memory.

That doesn't help, though. The capsule gets power cycled on EVERY access. It's not like it gets powered up, and then some 6502 code gets run from somewhere else, and then the capsule is read. While the 6502 code is executed from somewhere else, the capsule is powered down.

The reason modern flash take a long time to power up, compared to EPROMs, is that they actually have a fairly complex state machine or microcontroller inside that manages write and erase cycles. However, that controller has to initialize itself at power up before even reads are possible. EPROM and masked ROMs didn't have any of that.

Anyhow, since I have not actually tried modern flash chips with the HHC, by all means please take my statements here with a grain of salt, and actually try it. Given that the CMOS will try to power itself through the ESD protection diodes of the address and data lines, maybe it will stay alive and work.