Panasonic HHC ROM 'capules'

[Jeff_Birt]

I will know more about the ROM access time in a few days when I get a chance to look at it. What occurs to me though is that Panasonic instituted the /8 of PHI0 for this reason. The OS has to set that register in the Y-Driver chip. Then proceed to do what else it needs to do before trying to actually read from the ROM. It seems Panasonic must have had this in mind too, but the proof will be in the pudding, or testing in this case. The 'short circuit' of the ROM power still bugs me too, given that most of them have a 0.1uf cap strapped across the power rails it seems a terrible waste of power.

I used Fusion 360 to create the model. I printed a sample last night which came out pretty good. It fit even though the filament used is not ideal. There are a few minor tweaks left, then I'll try a PCB carrier. I also need to try and rig up a way to plug this style carrier into a Molex 78802 socket. This is the typed used on the TRS-80 Model 100 and I have spares. This will allow building an adapter PCB to program the EPROMs in situ on the carrier.