HP19C - Behaviour of the ACT Processor Status Bits

[Mike T.]

I'm trying to get my head around the way the processor status bits behave on the HP19C and while I think I have figured some of it out I suspect I have not managed to get my head around all the interactions between the switches, the PIK chip and the status bits so I the following summary is probably incomplete at best or just down right wrong if I've understood some things incorrectly.

- If I have followed the discussion from another thread (that I can't find anymore) then when S(0) is set the MAN/TRACE/NORM switch sets S(3) when in the MAN position and clears it otherwise, If S(0) is cleared the switch position has no effect on S(3).

- I believe that S(15) is used to indicate that a key has been pressed, and that on the HP19C when S(0) is set S(15) is cleared by the PIK chip to indicate that there is a key press waiting in the input buffer. I don't know if S(15) is updated by something else when S(0) is cleared.

- And I think that as with other woodstock models S(5) is used to indicate low battery state.

Any additional information about other external inputs that set or clear any of the processor status bits and any corrections to the above summary would be very helpful.

Thank you.