New Saturn asm "add loop" benchmark for the HP48G
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10-31-2023, 01:31 AM
Post: #9
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RE: New Saturn asm "add loop" benchmark for the HP48G
(10-27-2023 07:26 AM)Werner Wrote:(10-26-2023 05:24 PM)Jonathan Busby Wrote: D'oh! Very clever Once again I am blinded by my monomania, this time directed towards the custom interrupt routine -- I hadn't given the inner add loop a second thought in terms of performance. In a perfect world, the "C=C+1 WP" instruction would only take two cycles to decode -- and that's what I overlooked. Already at P = 4 , the cycle time of "C=C+1 WP" equals the 7 cycles ( ignoring memory access considerations ) of the "C=C+1 A" instruction. If you really want to go nuts, you could unroll the increment code for the B field in a variation on J-F Garnier's code Your original A field code brings the count up to around 4382026. So, a few hundred thousand more, but I was hoping for something more dramatic considering the code for an unoptimized HP-71B assembly language add loop, which runs ats 640KHz, reaches over 1E6 in 60 seconds. Anyways, it seems my ISR code is bugged ( the IRAM reconfiguration code is flawless ) in some strange way which I still trying to work out ( it doesn't help that I have chronic sleep deprivation ( really ) and I got up at around 4 AM today ). So, I left out checking for C.A overflow when TIMER2 generates an interrupt. This means it's *possible* that an interrupt could corrupt the count, but it's unlikely, and you'd know it if it happened -- I plan on having this fixed soon. Quote:Cheers, Werner Regards, Jonathan Aeternitas modo est. Longa non est, paene nil. |
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