New Saturn asm "add loop" benchmark for the HP48G
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11-01-2023, 07:30 PM
(This post was last modified: 11-01-2023 08:09 PM by Jonathan Busby.)
Post: #12
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RE: New Saturn asm "add loop" benchmark for the HP48G
(11-01-2023 06:48 PM)brouhaha Wrote: Possibly memory controller behavior. Well, the cycle reference I used was supposed to take into account the SRAM instruction and data fetch and the extra cycles incurred by the Saturn bus. Quote:The memory controller is not well doscribed in any public documentation, I thought the Saturn bus was pretty well described in the HP-71B various internal design specs, including the daisy-chained memory controllers. But, if your talking about the internals of the Yorke memory comntroller(s) and eg. why there are quarter cycles, then there's very little information. Quote:but it matches the 4-bit Satun bus to 8-bit memory, Well, the minimum read cycle time for the Yorke is 1000nS . But, since bytes are fetched, the effective frequency is 2MHz which is the speed of the memory controllers and the Saturn bus. Quote:and depending on the memory access pattern can introdue delays. Well, the access pattern on the Saturn bus for the inner add loop is :
(1) I'm not sure if these bus operations take place -- if the Yorke Saturn is designed well then they shouldn't, which means my final cycle count could be off by six... So, in addition to the execution time, the Saturn bus introduces five ~2MHz cycles of overhead, which equates to ten ~4MHz cycles. Quote:Perhaps a tight loop is a case where that happens. Thanks for the tip I need to investigate this... Quote:You might try unrolling the loop a bit, perhaps by putting two or four increments consecutively, and see whether the overhead is lower. Good idea I think I'll do a 256 instruction unroll of the B field increment operation with a modified version of J-F Garnier's code. Regards, Jonathan Aeternitas modo est. Longa non est, paene nil. |
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