WIP: 16C firmware hack for more memory

[brouhaha]

(11-28-2023 03:40 PM)blackjetrock Wrote:  I've just found out that running code in the space of a single instruction is an old idea:
https://en.wikipedia.org/wiki/Atlas_(com...#Extracode

There have been machines that stored multiple instructions in one word, but Atlas, despite being very influential on later processor architectures, was not one of them. The CDC 6600 was a notable such machine, introduced in 1964. The CDC 6600 central processor packed 15-bit and 30-bit instructions into a 60-bit machine word. The IBM 7030 ("STRETCH", 1961) used 32-bit and 64-bit instructions, but could directly address the 32-bit instructions, so it was not really the same concept.

Atlas Extracodes were subroutine call instructions, and were the same size as other Atlas instructions. Quoting that Wikipedia article:

Quote:If the uppermost bit was set to one, this was an Extracode and was implemented as a special kind of subroutine jump to a location in the fixed store (ROM), its address being determined by the other nine bits. About 250 extracodes were implemented, of the 512 possible.

Extracodes were what would be called software interrupts or traps today.

The subroutine call was arguably invented in 1842, though not implemented at that time. In modern times, it can be considered to have been invented in 1946. The original purpose of the subroutine was in fact to save memory. Mark Smotherman's web site gives a lot of historical information on computer architecture, including this history of subroutines:

https://people.computing.clemson.edu/~ma...tines.html

The IBM System/360 (1964) SVC (supervisor call) was similar to an Atlas Extracode, though the call was to main memory, and wasn't typically used for mathematical functions.

The DEC 36-bit machines, starting with the PDP-6 (1964) had UUO instructions, "Unimplemented User Operations", which were essentially the same as Extracodes. These were divided into User UUOs, which callec a subroutine at the current privilege level, and Monitor UUOs, which trapped to supervisor mode, like the IBM 360 SVC.

It is my understanding that the IBM 360 SVC and DEC UUOs were inspired by Atlas.

Any processor with an undefined instruction trap effectively has the equivalent of the Extracode.

What has, AFAIK, never existed, is a processor that packs multiple n-bit instructions into a single n-bit data word. The closest thing I know of is the OPR ("operate") instruction of the DEC 18-bit and 12-bit processors (e.g. PDP-8). Individual bits in the encoding perform distinct operations and can be combined, thus you can have an instruction to complement the accumulator, complement the link flag (carry), or do both in one instruction (possibly with additional operations as well). This was called "microcoding", by analogy to horizontal microcode,. The combination of functions performed is, however, considered to be a single machine instruction.

The HP calculator microarchitectures do, of course, have subroutine calls. In a simulator, it is possible to use otherwise unassigned opcodes to implement more specialize subroutine calls. But then, in the simulator one could simply interpret an undefined opcode to perform any desired operations in native code. HP's ARM-based 12C and 15C do that. Alternatively, a simulator can trap micrpinstruction fetches from specific microcode addresses, without changing the microcode ROM image at all, which is what I did in the 41C version of the ARM-based 41CV prototype Rich Ottosen and I developed, I order to provide four-level stack display, 100 flags, etc.