HP35 - A&R and C&T chips - How is the Pointer communicated?

[van2z]

I love building emulators, on a low level. Not just simulating how they should function on the outside, but emulating each chip in detail, accurately timing and handling all of the inter-chip.

I have been eying the HP35 with its split CPU functionality with interest. I found the archive of Jacques Laporte's website very useful. However there is one part that continues to confuse me.

The CPU is basically broken down into two chips. The Control & Timing (C&T), and the Arithmetic & Register (A&R).

The C&T chip owns the Pointer register P. Whenever a Type 4 instruction comes up, the C&T chip will update register P accordingly.

However, the A&R chip is somehow supposed to access this register too.

For Type 2 instructions, A&R looks at the Word Select (WS) to determine which part of the register is being updated. In some cases, it would need to use Pointer. But the pointer lives on the C&T chip, not the A&R chip. How is that supposed to be transferred?

Checking further, for Type 5 instructions, the A&R is has an instruction to load an immediate into register C, and then decrement the Pointer. How is it supposed to decrement the Pointer? The Pointer is owned by C&T...

Checking the schematics (1, 2) it is not at all obvious to me, how is this pointer copied between the two chips? The only communication I can tell between the two chips is just sending over the WS and the Carry. No pointer...