What if?

[Joseph_21sv]

Beyond that first problem that you see, Paul, the problem I have realized is that while my idea may be a complete thought, it does not mean what I had intended it to mean. You see, it slipped my mind that it can mean that there is also a bit-sliced address bus, and it radically changes the character of the situation if it does, as I meant it to, for then each individual CPU can have private access to one slice of a wider common address bus, which will mean that the two CPUs do not contend priority access to the bits of the narrower address bus of an individual CPU.
In the real world, it is only during the later end of the 32-bit era that DRAM has come to be thought of as "generally very slow" compared to a CPU (a late model Pentium II could be clocked over 500 MHz while the SDRAM it was supporting could not have an I/O bus clock faster than 200 MHz). Therefore, caches of SRAM started to be built into the CPUs themselves so as to avoid incurring delays by making them access slow SDRAM every time they needed to fetch data. 8 and 16-bit CPUs never really needed or need caching because their heyday was in the days when, for the most part, you could even expect a computer to have a CPU that was very slow compared to its DRAM and moreover the heyday of 8-bit CPUs was so early in computing history that most logic and memory chips simply could not switch fast enough to make it easy to time-division multiplex CPU and VDU accesses to DRAM, a problem most computers of the day solved either by having a register that the VDU's logic would rewrite every time the raster switched into and out of the blanking period (the CPU could read this register and see when it was safe to write to the screen). However, this had the disadvantage that it relied on the CPU not being told in software to simply ignore that register and try to write to the screen anyway, but the designs must have been done trusting that software developers would not purposefully have that happen. Ultimately though, this only ever applied to the cheaper models of those days, expensive enough ones already having a video adapter with separate memory for the VDU to read from or faster logic and memory chips so that it was easier or even effectively unnecessary to time-division multiplex CPU and VDU accesses to DRAM and moreover these technologies became cheaper to deploy fast enough that computer designers simply ceased designing new computers with the slow chips for which the status register trick was necessary in order to cut costs associated with manufacturing them and nobody really missed them either, having known firsthand what the computers with these chips were like. For my part, I have really known no computers like that firsthand, so I cannot say that I really either prefer for CPU and VDU accesses to DRAM to be easy, hard or effectively unnecessary to time-division multiplex, but I do not expect to prefer the path of greater resistance if I ever really get to know what it is like..