HP-48 FRAM Cards

[Dave Frederickson]

Scott,

I agree that read/write cycles wear out FRAM, but there's a difference. Read cycles wear out a device, so that can be called "destructive read". FRAM also employs a write-after-read architecture which could be called a "destructive read architecture". It could be called this because in order to read the device it must erase the data first, hence "destructive read" architecture. Because FRAM uses a destructive read architecture is no grounds for dismissing the technology as inferior. On the contrary, even though a write-after-read architecture has more read/write cycles per data access compared to flash, it wears out at a much lower rate. FRAM can endure more than 10 billion times the number of write cycles as flash. Plus, FRAM is nonvolatile.

So because of the architecture you find FRAM less desirable for the 48SX/GX, despite the much greater endurance and not requiring a battery.

Personally, the architecture doesn't bother me.

(07-23-2016 03:14 AM)snrowe Wrote:  The link Sylvain posted agrees with other sources I read up on FRAM has a read/write limit somewhere between 1-10 trillion cycles. While this is certainly a lot of cycles, when this is applied to a program constantly running off the card It could theoretically become an issue in a couple of years depending on duty cycle of memory access.

You call 150,000 years of continuous data logging "a couple"? Compare that to less than 7 minutes for flash.

Dave