HP-48 FRAM Cards

[Hans Brueggemann]

(03-23-2017 02:45 PM)Han Wrote:  I still am not quite clear on the read/write cycles. While there may be more than 10 billion times the number of cycles as FLASH (according to an earlier post), what exactly happens during a read cycle? Does the entire content of FRAM get re-written? Or just the bits that got read? What happens when FRAM gets mapped to parts that get read frequently? For example, if the display data is mapped onto FRAM, then there are lots of read/write cycles without the user ever doing anything but having their calculator on. Can someone comment on this?

you can do the math, here the excerpt from FRAM71B's (a memory extension for the HP-71B) user manual concerning FRAM endurance, as an example:

"FRAM71B uses Fujitsu MB85R4M2T FRAM that has a read/write cycle endurance of 2 x 10^13 8-bit cycles. FRAM71B has to convert each nibble-write cycle of the HP-71B into two byte-
wide access cycles (read-modify-write) for the FRAM. The standard clock speed of your HP-71B is approx. 640 kHz, which results in a maximum of 470 x 103 FRAM-byte-accesses (FBA) per second. This is the highest sustained access speed that the HP-71B can reach. Thus, your HP-71B's minimum operating time to wear out the FRAM is
T = 2 x 1013 cycles / 470 kFBA / sec = 11820 hours."

hope that helps