Recreating Woodstock (67)

[Alejandro Paz(Germany)]

I have been very busy as of lately but did find the time to post the design files as promised.

Woodstock on an FPGA

I have been thinking about slowing the clock to 32 kHz, using an external oscillator, they are low power, much lower than the internal oscillator of the MachXO2, and increasing the throughput of the CPU from say 18 clocks for a 14-nibble opcode down to 4 clocks. This was achieved using a parallel ALU instead of a nibble-wise one. Logic count did go up like quite a bit !:

Design Summary
Number of registers: 672 out of 7209 (9%)
PFU registers: 671 out of 6864 (10%)
PIO registers: 1 out of 345 (0%)
Number of SLICEs: 1671 out of 3432 (49%)
SLICEs as Logic/ROM: 1671 out of 3432 (49%)
SLICEs as RAM: 0 out of 2574 (0%)
SLICEs as Carry: 194 out of 3432 (6%)
Number of LUT4s: 3259 out of 6864 (47%)


I'm still working on it, it doesn't have display output yet.