41CL Self-Update

[Monte Dalrymple]

(11-19-2017 09:49 AM)Neve Wrote:  I opened up the calc (again) and I checked for possible shorts between the CPLD connector and the female 2.5 jack mounted on the 3D port cover. No shorts there.
Just to be verify and be sure it’s not reversed, the ground wire on the CPLD side is the one closest to the FPGA connector, right? And it goes to the longest, curved middle tip on the 2.5 side.
If this is the case, I have it right.
The only thing that could be wrong, from my point of view, would be the reversed TX/RX on the 2.5 female jack.
However, Monte said that his method didn’t check for that....
Should I reverse them again? (Although I tried that earlier and it still didn’t work on the Mac)

I’m desperate....

If you have a voltmeter, pin 2 on the DB9 connector is TX. The metal "shell" on
the connector is ground. The voltage between pin 2 and GND is 0 when the serial
port is off. Executing SERON should make pin 2 go to about 5V. I don't remember
if it's plus or minus, but that doesn't matter, it's the presence of a voltage when
the serial port is on.