Nut Processor Information

[emece67]

I'm also reinventing the wheel, but instead of writing an emulator, I'm writing a synthesizable HDL description of the NUT processor in order to build a real machine around a FPGA. I know, Monte Dalrymple did it years ago, but as the TP said: What fun is a wheel if you didn't reinvent it yourself [twice]? To not repeat the very same thing, I'm using VHDL instead of Verilog and writing also a battery of testbenches in order to simulate the whole hp41 in a cycle accurate way. Surely this is a task Monte has also performed but, AFAIK, such code is not available.

The documentation you can find at TOS is highly valuable and a primary reference. If you do not know what TOS means, look inside this thread http://www.hpmuseum.org/forum/thread-9880.html .

As Mark has said, the Systemyde page (that's: Monte's page) is also really valuable, although, in my experience (I've seen it many times in students), the HDL description of some hardware is sometimes hard to cope with for people not used to the paradigms of such languages. The technical documentation of Monte's NEWT processor is really interesting and comprehensive.

Hope this helps, regards.