DM42: The internal view (hardware components)

[jebem]

(02-28-2018 06:00 PM)hth Wrote:  I am curious about the extra flash memory which I understand is on a serial bus.

Is it memory mapped into the ordinary address space and what kind of bus performance does it have compared to the built-in flash?

Håkan

That makes two of us...

The STM Reference manual for the processor contains huge information on the subject, but we do not know how the system was implemented by SwissMicros, as many working parameters must be set by the operating system to set the hardware intended behavior.

As far as I know, the STM processor uses a linear 4GB address space divided in eight 512MByte blocks, where all memory and peripherals are mapped.

I would expect a performance degradation when accessing the external Flash memory when compared to the internal Flash.
By how much, probably only after exhaustive testing can be determined.

This is a complex processor architecture, and there are many parameters that need to be set at low level in the O.S. depending on the designer goals.

For instance, the memory latency (wait cycles) must be set depending on the intended processor operation/speed/voltage settings and this applies to the internal Flash as well.
On the internal Flash a variable number of cycles is required depending on the type of code. Also STM offers instruction prefetch and cache to increase efficiency when accessing the Flash at higher clock speeds. These features need to be configured by software as well.

On the other hand the external Flash connected to the Quad-SPI processor interface can be accessed in a number of different ways, namely direct memory-mapped or indirect using registers or interrupt driven, different data word sizes can be accessed, etc.
Anyhow, the QUADSPI interface talks to the external Flash using 5-phase commands, and any one of these 5 phases needs to be set/skipped, so this introduce more indeterminacy on the performance. For example, the dummy cycles phase (wait cycles) can be used when operating the processor at higher speeds to let the Flash be ready for the processor.