Found these inside a non-working 71B

[Paul Berger (Canada)]

(03-12-2018 11:50 PM)Dave Frederickson Wrote:  I'm a bit confused by the daisy-chain diagram above. The "main 5 chips" are all daisy-chained, out to in, but according to the schematic, U5, the ROM, has it's DOUT unconnected and VDD is connected to DIN on both U5 and U6, the Port(0.1) RAM. Can you clairfy?

Dave

U5 is the OS ROM and is hard configured, it has to be that way as all the soft configured devices are given their address by the memory configuration routine, and that code would need to reside in a hard configured ROM. U6, 7, 8, and 9 are the base system RAM.

The connection between U6 Dout and U7 Din on the schematic extends on to a point W1 where it might be routed to the Din on the HPIL. I was under the impression that on the actual board it did not go any further that U7 Din but when I was looking at the actual board just now I saw the line that extends beyond U7 and ends up at an unconnected pad under U9. Who know what the purpose of that might have been.

Paul.