HP-41 MCode Question

[Sylvain Cote]

Thank you Ángel.

Next time I will do a test before asking questions, if I had done that I would had my answer right away.

Question 1 test

Code:

F000  001    XROM 1
F001  002    2 FUNCTIONS
F002  000    FCT:SCOTETST 1A
F003  08F    ADR: F08F
F004  000    FCT:TST
F005  093    ADR: F093
F006  000    NOP               
F007  000    NOP

TST body

Code:

F093  130  0 LDI       S&X              /// 
F094  1F0                               /// loading top main memory RAM chip register address offset 0
F095  270  p RAMSLCT                    /// selecting first RAM register of the top main memory RAM chip (1F0..1FF)
F096  038  8 RDATA                      /// read selected register (1F0) who currently is REG 00
F097  3F8    C=REG     F(e)             /// read last register (1FF) of selected RAM chip who currently is REG 15
F098  130  0 LDI       S&X              /// 
F099  1FF                               /// loading top main memory RAM chip register address offset 15
F09A  270  p RAMSLCT                    /// selecting last RAM register (1FF) of the top main memory RAM chip (1F0..1FF)
F09B  038  8 RDATA                      /// read selected register (1FF) who currently is REG 15
F09C  3B8    C=REG     E(d)             /// read one before last register of selected RAM chip (1FE) who currently is REG 14
F09D  130  0 LDI       S&X              /// 
F09E  010                               /// loading invalid register address
F09F  270  p RAMSLCT                    /// deselect RAM register
F0A0  3E0    RTN                        /// return

Setup before TST execution

Code:

SIZE 016
315 STO 15   /// located at RAM register 1FF
914 STO 14   /// located at RAM register 1FE
701 STO 01   /// located at RAM register 1F1
800 STO 00   /// located at RAM register 1F0

TST execution trace

Code:

F093  130  0 LDI       S&X     
F094  1F0                      ; C[S&X] = 1F0
F095  270  p RAMSLCT           ; RAM reg = 1F0
F096  038  8 RDATA             ; RAM read (C=08000000000002) from reg = 1F0 (subclass E)
F097  3F8    C=REG     F(e)    ; RAM read (C=03150000000002) from reg = 1FF (subclass E)
F098  130  0 LDI       S&X     
F099  1FF                      ; C[S&X] = 1FF
F09A  270  p RAMSLCT           ; RAM reg = 1FF
F09B  038  8 RDATA             ; RAM read (C=03150000000002) from reg = 1FF (subclass E)
F09C  3B8    C=REG     E(d)    ; RAM read (C=09140000000002) from reg = 1FE (subclass E)
F09D  130  0 LDI       S&X     
F09E  010                      ; C[S&X] = 010
F09F  270  p RAMSLCT           ; RAM reg = 010
F0A0  3E0    RTN               ; next PC = 00F0

Lesson learned from the above example:
1) RDATA always read current selected register (as you said)
2) RDATA has the same behavior of the non existent C=REG 0 if first register of a RAM chip is selected
3) C=REG 1 to 15 always return offset data from the current RAM chip selected

I still find it special (asymmetrical?) to create a WDATA and 16 x REG=C instructions and not do the same for the RDATA and C=REG counterpart.
It's not like they did not had free instruction slots to do it ...

Thanks again for the information Ángel.

Best regards,

Sylvain