How to test memory in an HP48 RAM card

[Jonathan Busby]

(01-21-2021 12:29 AM)mfleming Wrote:  Now that's a project I'd like to hear more about. I'd especially be interested in the serial <-> parallel bridge approach you use.

Well, the project is still in the design stage. The current problem I'm having is that even the "fast" ultra low power F-RAM chip made by Cypress Semiconductor has an SPI clock of only 40MHz. You might think that that's fast enough, *but* the clock period is 25ns. The reason this is a problem comes from the fact that one must issue one SPI opcode to the F-RAM chip before a read operation can take place. The problem is that each opcode is 8-bits ( one byte ). Furthermore, one also has to drive a three byte address onto the SPI bus. The problem comes from the fact that the HP48GX has about a 250ns setup time before the NCE chip select line is asserted. So, one has to sample the address bus on the HP48 side to detect an address change and the WE ( write enable ) line. When these lines settle, one has to transmit, *serially*, the 8-bit SPI read opcode, the three byte address and then the data before the NCE line is asserted,. This means that, when the HP48GX wants to read one byte, one has to transmit all the aforementioned signals on the SPI bus to the F-RAM device, which means that the minimum time taken by a read on the F-RAM side is : 25ns*8 + 25ns*8*3 + 25ns*8 = 1000ns , which is *WAY* over the maximum setup time for a read on the HP48 side.

Writes to the F-RAM chip have the same problem but it can be gotten around by some clever buffering. As for the reads, I don't think it's a fatal flaw and I am considering several ways to get around the problem, but I make no guarantees.

If the Cypress F-RAM chip had a, say, 192MHz clock instead of just 40MHz, then there'd be no problem. I've been in correspondence with a Cypress Semiconductor engineer, so we might find out if Cypress Semi is planning on releasing faster chips any time soon.

Regards,

Jonathan