New Saturn asm "add loop" benchmark for the HP48G

[Christoph Giesselink]

(11-05-2023 02:49 PM)Jonathan Busby Wrote:  Assuming the cycle counts from "Cycles du Saturn" are accurate ( which I doubt as they don't contain any half or quarter cycles due to Saturn bus NSTR cycle stretching ), then an estimated count for Werner's original non-unrolled add loop would be :

\( \dfrac{3900000 \cdot 60}{49} \approx 4775510 \)

This is 392325 larger than the actual count. Again, assuming the cycle counts I've been referencing are accurate, then this means something is stealing about (392325/60)*49 ~ 320398 cycles/sec . I know TIMER2, when running, steals a small amount of cycles for the purposes of keyboard polling every 1mS. Also, the card detect circuitry steals cycles while it's enabled. I'm dubious as to whether the aforementioned cumulative overhead steals ~320398 cycles/S, but I'm not sure. If the lower performance of my code can't be explained by taking the above into account, then we have a mystery.

Regards,

Jonathan

Have you thought about the UMA architecture sharing the main RAM between CPU und display controller in connection with the Clarke and York chip?

Not ony keyboard polling or card detection need some extra cycles, quote from the Clarke document: "The CPU is halted for 22-23 uS every 244 uS to read the data."

To avoid this, switch off the display during program execution.

(11-05-2023 02:49 PM)Jonathan Busby Wrote:  Assuming the cycle counts from "Cycles du Saturn" are accurate ( which I doubt as they don't contain any half or quarter cycles due to Saturn bus NSTR cycle stretching )

This is an extraction of the HP17BII =BPUTL source code. This code was designed to run on on the Saturn-ROM inside the Lewis chip or with different timing contants on an external 8-bit ROM chip.

The Saturn cycles are in [] where as the MEMC cycles are in ().

Code:


=BPUTL
...

*                                                 ---
BP10    B=A    S        (6)      Init f-counter      |     [4]
        OUT=C          (10)      Toggle beeper       |     [6]
        CPEX   2       (10)                          |     [6]
*                                   ---              |
BP20    CSL    W       (22)  NOP20     |             |    [20]
        CSR    W       (24)  NOP20     |             |    [20]
        B=B-1  S        (6)  Freq cntl |             |     [4]
        GONC   BP20  (14/7)            |             |  [10/3]
*                                   ---              |
        B=B+1  X        (8)     Incr dd*16; Done?    |     [6]
        GONC   BP10  (14/7)                          |  [10/3]
*                                                 ---
...

For thoose who may ask, sorry I don't have the complete HP17BII souece code, only the =BPUTL and =CHECKSUM implementations. Also no further information about the NSTR cycle stretching. The HP17BII entry point table is part of the Emu42 installer distribution so when runnung a HP17BII inside Emu42 you can easily jump to the =BPUTL code entrypoint in the Debugger.