(HP71B) RAM access in HP71B; how it works?

[floppy]

Hello,
I would like to understand how RAM is accessed in HP71B.
a) in the port of the card reader place
b) in the front ports

For this, I need few feedbacks from the community.
Depending of the gathered knowledge, I will update this post.
Except somebody has already an extensive documentation for RAM interaction or RAM emulation (probably already done at FRAM71B) and reading it would bring all answer
(now, I am reading the HW and SW IDS, Multimod PIC codes thanks to Mark Fleming,.. unfortunately FRAM71 stay closed like a mollusc shell).

So far I understood (please correct me if wrong).
a) Access of Card Reader RAM is similar to front port RAM for accessing RAM from the OS and its Bus
b) maximum 4*32KB RAM can be accessed in one Port
c) each RAM Module can have 1 to 4 RAM chips with their own local control chip (if hardware)
d) at power on, the HP71B look all ports, then depending of the feedbacks from the RAM control chips, it store the informations on his own in an area in order to remember it at next power on; a RAM map is then created by the OS
e) the RAM module dont store any data in it for own configuration; the HP71B OS store only in an own area

So far not seen:
- bus command for processing a new RAM configuration
- 1LJ4 chip = apparently a RAM control chip: was a reverse engineering done for understanding how it works?
- differences in command for addressing 1 to 4* 32KB RAMs
- how an 1LJ4 chip recognize this is the first ON (cold start) or this is a ON after a cold start

You see, a lot of questions. I will do my best to write the summary here. Except all is known, then I will delete that post (after receiving data with several informations).