HP9835 ROM questions

[Paul Berger (Canada)]

(07-10-2016 07:16 PM)dfnr2 Wrote:  

(07-10-2016 05:03 PM)Paul Berger (Canada) Wrote:  I can provide you with a pinout of the ROM slots but be aware that the logic level on those card slots is 6V which makes it somewhat inconvenient to use them with modern devices.

I would be interested in the pinout. Do you know what architecture the ROM modules use?

The ROMs are a custom mask programmed 8K byte NMOS chip. At the time they where designed an 8K byte ROM was bleeding edge.

Quote: As I understand, any module can go in any slot, without any conflict. Do they use relocatable code with each slot mapped to a fixed address, or is there decoding built into the modules, with each module at a fixed address independent of the slot?

The addressing is fixed however the address decoding resides on the ROM module, the address is likely set by the same mask that programs the data.

Quote: In a ROM replacement board, would the order of images in the EPROM make a difference?

As published yes, to change the order or mix of images in the EPROM the logic equations for two of the PLDs would need to be adjusted.

Quote:

Quote:What I did was create a card that plugs into one of the connectors for RAM cards which are the more usual 5V logic level. My design was posted on hpmuseum.net, http://www.hpmuseum.net/upload_htmlFile/...AMCard.zip unfortunately on the page it only mentions RAM card but the packages contains the documentation for my ROM card as well as a schematic for the 9835 64K RAM card. I have also built a RAM expansion card using more modern static RAMs so now my 9835A has a little over 512K of RAM. I have not put together any formal documentation for my RAM card yet. Both of these cards where constructed as hand wired prototype cards. If you have questions send me an email and I will assist.

Definitely interested in both RAM and ROM options. Do you by any chance have timing diagrams for the bus?

I have screen shots from my logic analyzer, that is how I figured out the bus signal timing. I did get some clues to what the signals on the bus did by reverse engineering the HP RAM card.

Quote: I looked at the RAM and ROM schematics. Is there a reason the RAM schematics seem much more complicated, or is it just that you reduced chip count by using PLD's in the ROM card?

The RAM card is more complicated for a few reasons.
1. It was built with mid 1970s technology so there is lots of discrete logic.
2. It uses DRAMs however the use of a DRAM controller chip simplified that.
3. It has logic to support it being the the block zero RAM card which has logic to map a chunk of the memory into block 1 for the virtual PPU.

But small PLDS are great for reducing chip count, I could have built the card using discrete logic but it would greatly increase the chip count and would make it much more difficult to change the order or mix of images on the EPROM. If I had used a CPLD I could probably have reduced the chip count to 2, a CPLD and an EPROM.

Quote:

Quote:I have no experience with the test ROM in fact this is the first time I have heard of anyone having one. If you have not already done so you should get the service manual from hpmuseum.net as it explains how to use the service ROM. I would be very interested in a dump of this ROM and can help you with dumping it.

I would love to dump it and will take any help I can get. The only thing is that when I plug it in, the machine looks dead on poweron. Perhaps an adapter can be built to probe the ROM with a microcontroller, without plugging in to the machine?

It would probably be pretty easy to to use different hardware to dump the ROM the other thing that can be done is watch what it does when the system starts up using a logic analyzer. The machine does have a facility built in to allow a ROM to take over control of the system on startup, which it appears the service ROM uses. The service guide did specify some key sequences to break out of the diag ROM and return to BASIC.

Quote:Thanks,

Dave

Paul.