Found these inside a non-working 71B

[MikeSD]

(03-12-2018 03:20 AM)Paul Berger (Canada) Wrote:  

(03-12-2018 02:58 AM)MikeSD Wrote:  I'm sure uou are probably right but this is far fewer than the way it was, since I had a FORTH too.

I'm not sure you are understanding how the 32K are wired, assuming both b are the same.
* what are the 8 connections you are referring to. There are the original 5 chips and I'm adding 2. With forth and Math there are 2 more there. So I'm confused about the connections.
* that said, there was a daisy chain error. I had Pin9 from bottom chip to pin 8 of the front chip. Should have been back chip. Pin9 of back chip wire in module to pin 8 of front chip. Then Pin9 of front chip goes to HPIL. Same results.

Assume that Vdd is pin 1 and ground is pin 13you should have Vdd and the next 6 (B3-B0, *str, and C/D) connected 1 for 1 with the U9 module plus pin 13 Gnd. The wire you connect to the via under the resistor is connected to the end of the chain it should go to pin 8 (Din) on the32K module that has that connection open, that same module should have a wire connecting pin 9 (Dout) to pin 8 of the next one and there is no need to connect Dout on the second one to anything.

The way this works is when initialized all the modules set Dout low, on this particular chain the first module has Din tied high. When the CPU send out a configure command the module with Din high answers with it information and when done it set its Dout high so then the next module in the chain gets configured and so on until no one responds at which time the memory configuration routine assumes it is done with that chain. The way it was wired in the picture with pin 8 of U9 connected to pin8 of one of the 32K modules Din would get raised on both of them at the same time and that will not work, so just remember Dout to Din all through the chain. Pins 1 to 7 and 13 get connected straight 3 and pins 10 to 12 are not used by RAM or ROM modules but they are there because the modules are designed so that they can be put into a front side plugin and those connection are on the 4 front ports and the HPIL port but are used by plugins other than normal RAM or ROM modules.

Paul.

I think i have the wiring right now. The wire that was on pin8 of the front chip is now on pin8 of back chip. Pin 9 on back chip is connected to pin jumper to pin 8 of front chip. Pin 9 of front chip goes tp HPIL pin 8 line. A problem still exists because u9 pin 9 is also connected to HPIL line. This has the effect of tying both pin 9s together. Not sure i can just leave pin 9 open on last RAM chip. The calc this was on had the line between u9-Pin9 and HPIL pin 8 line cut. This 71b hasntnhad that line cut, yet.

This is what I was shooting for. But I haven't made that cut yet, so you see the problem. I just lifted the last wire, from Front RAM-9 but thst didnt help. Looks like I might have to make that cut on my test 71B.

Once this is done, and if it works, will the 64K be port RAM or system RAM after powering up?