HP41CL newbie question

[Monte Dalrymple]

(03-15-2018 05:10 PM)Neve Wrote:  But still having the same LASTx issue (from my other post).
http://www.hpmuseum.org/forum/thread-10303.html

I just disassembled CLUTILSB1 and can see that the LAST X registers is used
during the CALC_ON polling point for temporary storage. That's the source of
your problem. 'Angel will need to update the code to fix this issue. It should
be as simple as using a CPU register instead of LAST X, but that's just my
guess.

Assembled boards for the Time Module are sitting in the corner of my office.
I haven't had time to try programming the FPGA on one to see if I've screwed
up something.