[41CL WARP] XEQ+ oddness

[Monte Dalrymple]

(04-11-2021 02:12 PM)Sylvain Cote Wrote:  41CL boards from Monte Dalrymple:

1. ENBANK1 to ENBANK4 are supported (aka ENROMx, 0x100, 0x180, 0x140, 0x1C0)
2. page & bank mapping are done with the WCMD NEWT instruction and with the MMU (0x804xxx adresses)
3. extended 16 bits NUT instruction structure
   
   1. bits 15 to 14 unused (should/must be set to zero ?)
   2. bits 13 to 12 used for turbo handling (bits = this/next instruction)
      • 00 = turbo execute / turbo fetch (if enabled)
      • 01 = normal execute / normal fetch
      • 1x = refetch, normal execute / normal fetch
        
   3. bits 11 to 10 unused (should/must be set to zero ?)
   4. bits 9 to 0 are for NUT instructions
      
4. pages that are bank switch enabled
   
   1. some lower pages are standalone (0x4, 0x5)
   2. some lower pages are linked (0x6/0x7)
   3. even/odd port pages are linked (0x8/0x9, 0xA/0xB, 0xC/0xD, 0xE/0xF)
      
5. OS pages are not bank switch enabled (0x0, 0x1, 0x2, 0x3)
   

Some corrections:

[*]bits 15 to 14 unused (ignored)
[*]bits 11 to 10 unused (ignored)
[*]some lower pages are standalone (0x4, 0x6, 0x7)
[*]some lower pages are linked (0x3/0x5)
[*]OS pages are not bank switch enabled (0x0, 0x1, 0x2)

The 0x3/0x5 linking is required by the CX Extended Functions. The bank is switched by code in page 3 before a jump to code in page 5.