SR-52 and subroutine levels.

[Didier Lachieze]

(05-27-2022 11:07 PM)Gene Wrote:  The SR-56 had 100 steps and 10 data memories. Maybe that meant another subroutine level stored. Don't know.

The SR-52 has two return pointers (from first-level subroutine to main program and from second-level subroutine to first-level subroutine). Assuming the return pointer is the step number to return to, this means 6 digits to store (2x3 digits).
As the SR-56 has only 100 program steps (00 to 99) the SR-52 6 digits return pointers can now store 3 return addresses (3x2 digits), so you get one more subroutine level with the same internal memory footprint.

(05-27-2022 11:07 PM)Gene Wrote:  The SR-56 had fewer than 64 op codes built in, making me wonder if it was a six-bit machine.

I don’t think so. The SR-56 uses a single TMC0599 Multi-Register Chip which contains 30 registers (vs. two on the SR-52).
With 8-bit instructions the 100 steps fit in 13 registers (in fact 104 steps fit in 13 registers but the last 4 are not accessible due to the two-digit step number limitation).
Then you add 10 user memory registers which leaves 7 registers available for the 7 pending operations on the SR-56 (down from 10 on the SR-52).
With 6-bit instructions the 100 steps would fit in 10 registers and the SR-56 would have kept the 10 pending operations of the SR-52, but this would have meant a significant change on the memory program mapping logic to the memory registers and TI may have decided that it was not worth for 3 more pending operations on their entry level programmable calculator.