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HP-15C: Fixing the CHS and Stack Lift Bug
01-13-2023, 10:51 PM (This post was last modified: 03-07-2023 07:03 AM by brouhaha.)
Post: #29
RE: HP-15C: Fixing the CHS and Stack Lift Bug
(12-28-2015 11:14 PM)Thomas Klemm Wrote:  What I don't understand is the line numbering in 15c.obj:
0000-17ff
2000-37ff

Any ideas as to why there's a gap?

Until 1988 when HP updated the Voyager electronics to use the newer SST chip ("Single-chip Series Ten", 1LQ9, see Chuck McCord's HHC 2022, HPCC 2022, and Allschwil 2022 presentations), the Voyager calculators used a 1LF5 (later 1LM2) Nut CPU and a 1LE2 (later 1LH1) R2D2. The R2D2 chip provides 6144 10-bit words of ROM, 40 56-bit words of RAM, and the LCD display driver. That was sufficient for all models but the 15C. In fact, the 10C only used 4096 words of ROM and 24 words of RAM, and at onee time there was consideration to making a cost-reduced R2D2 that would only have that much memory.

The ROM of the R2D2 is normally addressed to start at 0x0000, so it ends at 0x17ff. The RAM is split into two sections, from 0x00 through 0x07 (mostly used for the RPN stack, temporaries, housekeeping), and 0xe0 through 0xff (mostly used for numbered user registers, the user program, and more housekeeping). The LCD is bit-mapped at RAM addresses 0x09 and 0x0a. There is a hardware register of some kind, which might be a sleep timer, at 0x08.

The 15C needed more memory, so it was designed to use two R2D2 chips. The LCD controller of the second one is not used, so it is disabled, and the pins for it are not bonded out, allowing it to be packaged in the smaller square QFP package like the Nut CPU. In order to have two R2D2 chips, the memories needed to be in diffeerent address ranges. The 1LE2 wasn't designed for that, but the newer 1LH1 R2D2 was. It could have different base addresses fro the RAM and ROM mask programmed. It supported at least one alternate address setting, which is used by the 1LH1-0302 in the 15C. The ROM is from 0x2000 to 0x37ff, the small RAM block is from 0x10 through 0x17, and the large RAM block is from 0xc0 through 0xdf.

The 10C was discontinued before the SST chip was used, but the 11C, 12C, 15C, and 16C were redesigned to use the 1LQ9 SST chip (with four different ROM masks). The SST incorporated the functionality of the Nut CPU and one R2D2 chip, so in the 11C, 12C, and 16C the 1LQ9 was self-contained, forming a true Single-chip Series Ten. In the 15C, the 1LQ9-0325 was configured to communicate with the second R2D2, the 1LH1-0302, as was used in all 15C variants through its discontinuation. (The 15C LE hardware is entirely different, based on the Atmel AT91SAM7L128 ARM microcontroller.)
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RE: HP-15C: Fixing the CHS and Stack Lift Bug - brouhaha - 01-13-2023 10:51 PM



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