Recreating a HP-25

[Alejandro Paz(Germany)]

Thanks !

Elaborating a bit on the inner workings, the first I can say is that it is not HW-compatible.

* Arithmetic/data operations are nibble-based: opcodes that work on all 14 nibbles take 33 cycles.
* Two cycles to access registers, it simplifies things. Registers are in a dual-ported RAM. (2-phase clocks in FPGAs are... not the best approach).
* Microcode resides in a ROM.
* Decoding is done using behavioral constructs, no single gates. (Using single gates could reduce gate count).
* ADD/SUB is done using behavioral models, no ROM-based ALU (like the original, ROMs were easy and fast).
* A couple of opcodes are still missing .
* The display works differently, in my case it has access to A&B simultaneously.

If you have GTKWave handy, you could load dump.vcd, and see (pretty signals) how it works

The keyboard module is not there yet. I was thinking on doing hw-debouncing, it is going to need some counters, one per key would be ideal..., scanning slowly like at 50 Hz or so reduces the number of bits in the counters, maybe I can get aways with 2 bits...

Regarding speed... it can do 20 MHz on this low power part... Amazing what HP did with like 300 kHz

Here is the output of Diamond's mapper:
---------------------------------

Design Information

Command line: map -a MachXO2 -p LCMXO2-1200ZE -t TQFP144 -s 1 -oc Industrial
WS_WS.ngd -o WS_WS_map.ncd -pr WS_WS.prf -mp WS_WS.mrp
C:/02_Elektronik/084_Woodstock/05_Lattice/WS.lpf -c 0 -gui
Target Vendor: LATTICE
Target Device: LCMXO2-1200ZETQFP144
Target Performance: 1
Mapper: xo2c00, version: Diamond (64-bit) 3.5.1.302
Mapped on: 06/09/16 13:57:02


Design Summary
Number of registers: 210 out of 1604 (13%)
PFU registers: 210 out of 1280 (16%)
PIO registers: 0 out of 324 (0%)
Number of SLICEs: 368 out of 640 (58%)
SLICEs as Logic/ROM: 368 out of 640 (58%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 32 out of 640 (5%)
Number of LUT4s: 732 out of 1280 (57%)
Number of logic LUTs: 668
Number of distributed RAM: 0 (0 LUT4s)
Number of ripple logic: 32 (64 LUT4s)
Number of shift registers: 0
Number of PIO sites used: 43 + 4(JTAG) out of 108 (44%)
Number of block RAMs: 4 out of 7 (57%)
Number of GSRs: 0 out of 1 (0%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)


Preference Summary

FREQUENCY NET "clk_in_c" 36.380000 MHz (4096 errors)

4096 items scored, 4096 timing errors detected.
Warning: 20.929MHz is the maximum frequency for this preference.