HP-41C Bank Switching Schemes [2020-03-25]

[Sylvain Cote]

This article is trying to explain how each HP-41C bank switching peripherals & modules works.

After reading bank switched capable devices documentation and with the help of our devices/mcode guru: Monte, Diego, Meindert, Ángel, Håkan, etc., I have gathered the following information.
This is a work in progress, missing devices will be added as I finish reading manuals and get confirmation of my understanding from the devices creators when possible.

Sylvain

CMT-10-16KB packaged in a module shell:

1. unit specifications:
   
   1. released in September 1985
   2. uses a 27C256 EPROM (256k bits = 16k x 16 bits words)
   3. splitted into four 4K (x16 bits) blocks (0 to 3)
      
2. extended 16 bits NUT instruction structure:
   
   1. bits 15 to 13 must be set to zero
   2. bits 12 to 10 are for blocks switching
      
      1. bit 12 set to 1 indicate to the module internal firmware/hardware to interpret bits 11 and 10
      2. bits 11 & 10 indicate the following: 00 = block 0, 01 = block 1, 10 = block 2, 11 = block 3
         
   3. bits 9 to 0 are for NUT instructions
      
3. bank switching can also be done with 16 bits modified ENBANKx/ENROMx instructions:
   
   1. ENBANK1/ENROM1: 0x100 or 01 0000 0000 becomes 0001 0101 0000 0000 or 0x1500
   2. ENBANK2/ENROM2: 0x180 or 01 1000 0000 becomes 0001 1001 1000 0000 or 0x1980
   3. ENBANK3/ENROM3: 0x140 or 01 0100 0000 becomes 0001 1101 0100 0000 or 0x1D40 (not in the manual but can be extrapolated)
   4. ENBANK4/ENROM4: 0x1C0 or 01 1100 0000 (not in the manual and not supported)
      
4. bank switching behavior:
   
   1. bank 1 even/lower page always contains 4K block 0
   2. bank 1 odd/higher page often contains 4K block 1 (at boot up, mode changes, etc)
   3. bank 1 odd/higher page is changed to the specified block (0 to 3) when the module encounter an instruction with block switching bits set
   4. bank 1 odd/higher page is changed to the specified block (1 to 3) when a modified ENBANK1 to ENBANK3 instruction is interpreted
      
   
   

ZEPROM packaged in a module shell:

1. unit specifications:
   
   1. released in 1987
   2. 16K EPROM (not specified but probably uses a 256k bits EPROM like the 27C256)
   3. can be configured as 16K flat or as two banks of 8K
      
2. bank switching instructions:
   
   1. ENBANK1/ENROM1 and ENBANK2/ENROM2 are supported (0x100, 0x180)
   2. ENBANK3/ENROM3 and ENBANK4/ENROM4 are not supported (0x140, 0x1C0)
      
3. bank switching behavior:
   
   1. ENBANK1/ENROM1 activate the first 8K (even/odd pages)
   2. ENBANK2/ENROM2 activate the second 8K (even/odd pages)
      
   
   

Clonix/NoV packaged in a module shell:

1. units specifications:
   
   1. Clonix 41 module was released in December 2003
   2. Clonix 41: 24K Flash
   3. Clonix-D: 48K Flash
   4. USB-41: 48K Flash (82143A emulation on Windows over USB)
   5. NoVRAM: 16K FRAM & 24K Flash (8K Flash available)
   6. NoV-32: 32K FRAM & 24K Flash (8K Flash available)
   7. NoV-64: 64K FRAM & 48K Flash (32K Flash available)
   8. NoV-64d: 64K FRAM & 48K Flash (32K Flash available)
      
2. Flash bank switching instructions:
   
   1. ENBANKx/ENROMx 1 to 4 are supported (0x100, 0x180, 0x140, 0x1C0)
   2. page & bank mapping is done with ClonixConfig Windows utility
      
      1. a non-bank switch ROM image is mapped to all the other banks of the same page
         ex.: the MATH ROM is mapped to banks 1, 2, 3 & 4 of the page it is mapped to
      2. bank switch ROM image is mapped to all the other banks according to the bank switch behavior (2 banks or 4 banks scheme)
      3. a 2 banks scheme ROM will map bank 1 to bank 1 & 3 and map bank 2 to bank 2 & 4.
         ex: Advantage ROM even page is mapped to banks 1, 2, 3 & 4
         ex: Advantage ROM odd page bank 1 is mapped to banks 1 and 3
         ex: Advantage ROM odd page bank 2 is mapped to banks 2 and 4
      4. a 4 banks scheme ROM will map each banks to their expected locations (B1>B1, B2>B2, B3>B3, B4>B4).
3. Flash bank switching behavior:
   
   1. a bank switch in Clonix/NoV module switch all pages of that module to the selected bank
      ex.: ENBANK3/ENROM3 executed in a Clonix/NoV module activate bank 3 for all pages (from 0x4 to 0xF at the same time) for that module
      
4. RAM bank switching instructions:
   
   upcoming
   
5. RAM bank switching behavior:
   
   upcoming
   
   
   

MLDL2000 packaged in a card reader shell:

1. unit specifications:
   
   1. released in June 2005
   2. SRAM: 512K x 16 bits (s/n >= 2050)
   3. SRAM: 1M x 16 bits (s/n < 2050)
   4. Flash: 1M x 16 bits (Flash can contain up to 255 ROM images)
   5. firmware v1.51: support bank switching from page 0x6 to page 0xF
   6. firmware v1.70: support bank switching from page 0x0 to page 0xF
      
2. bank switching instructions:
   
   1. ENBANKx/ENROMx 1 to 4 are supported (0x100, 0x180, 0x140, 0x1C0)
      
3. Bank switching behavior:
   
   1. even/odd pages are linked (0x6/0x7, 0x8/0x9, 0xA/0xB, 0xC/0xD, 0xE/0xF)
   2. lower pages bank switching (0x0 to 0x5) is not explained
      
   Note: update coming soon for this device.
   

41CL board replacing a fullnut board:

1. unit specifications:
   
   1. beta board was released in November 2011
   2. 41CL v2: 512 KB SRAM & 2 MB Flash (Flash can contain up to 256 ROM images)
   3. 41CL v3: 1 MB SRAM & 4 MB Flash (Flash can contain up to 512 ROM images)
   4. 41CL v4: 1 MB SRAM & 4 MB Flash (Flash can contain up to 512 ROM images)
   5. 41CL v5: 1 MB SRAM & 8 MB Flash (Flash can contain up to 1024 ROM images)
      
2. extended 16 bits NUT instruction structure
   
   1. bits 15 to 14 unused (reserved, currently ignored)
   2. bits 13 to 12 used for turbo handling (bits = this/next instruction)
      
      1. 00 = turbo execute / turbo fetch (if enabled)
      2. 01 = normal execute / normal fetch
      3. 1x = refetch, normal execute / normal fetch
         
   3. bits 11 to 10 unused (reserved, currently ignored)
   4. bits 9 to 0 are for NUT instructions
      
3. bank switching instructions:
   
   1. ENBANKx/ENROMx 1 to 4 are supported (0x100, 0x180, 0x140, 0x1C0)
   2. page & bank mapping are done with the WCMD NEWT instruction (0x1FC) and with the MMU (0x804xxx adresses)
      
4. Bank switching behavior:
   
   1. OS pages are not bank switch enabled (0x0, 0x1, 0x2, 0x3)
   2. some lower pages are standalone (0x4, 0x6, 0x7)
   3. pages 0x3/0x5 are linked, but only 0x5 is actually bank switched
   4. even/odd port pages are linked (0x8/0x9, 0xA/0xB, 0xC/0xD, 0xE/0xF)
   5. each standalone page or linked pages are bank switched independently from each other
   6. all bank selects are returned to select Bank 1 when entering Deep Sleep because the FPGA is powered down when the calculator is off.
      
   
   

W&W devices

upcoming

DM41X

upcoming

edit: typo