DM42 PSE bug test... . ....
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07-03-2020, 01:44 PM
Post: #1
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DM42 PSE bug test... . ....
I would like have others verify this bug I have found in the DM42.
I am particularly interested if this bug exists in other versions of the OS (3.17, etc...) I have some code that simply steps through (all 100) REG memories; recalling the memory location (in Y) and memory contents (in X). This is a simple loop, terminated in ISG of the counter and jumps back to the recall and Pause (PSE) loop. IF RefLCD is set to 0, the code stops before the PSE. I do understand that RefLCD = 0 should not refresh the display, but this actually stops the code from executing. I have posted this in the DM42 forum and it has been verified there; I am curious if it is sensitive to DM42 OS level. When RefLCD is set to zero, this codes does not run; it stops after the PSE statement: (it assumes that REGS is set to 100 - please adjust for your situation) ++++++++++++++++++++ LBL RCLMEM 0.09901 STO "CTR" LBL 03 RCL "CTR" IP RCL IND "CTR" PSE ISG "CTR" GTO 03 RTN ++++++++++++++++++++ Regards, TomC |
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