HP48G Clock Variability

[KeithB]

The whole point of the PLL is that, because of the feedback, the VCO does not need to be accurate, The crystal accuracy should be setting the frequency accuracy

[Jonathan Busby]

(02-11-2021 09:32 PM)KeithB Wrote:  The whole point of the PLL is that, because of the feedback, the VCO does not need to be accurate, The crystal accuracy should be setting the frequency accuracy

My point exactly : If the clock is variable, and from my experience the crystal oscillator is usually *not* variable, then something "weird" is going on with the PLL, perhaps with the VCO, phase detector or low-pass filter.

Regards,

Jonathan

[Giuseppe Donnini]

(02-06-2021 03:00 PM)TomC Wrote:  While there may be long term variability due to temperature, the variability I am referring to is the short term variability one can see doing the <ON><D> testing.

The following message by Dave Arnett—sent to comp.sys.hp48 on August 24th, 1995 (Google Groups Link)—might help answering your question:

> How is this speed measure done anyway? Does the HP-48 have two clocks built
> in where the bus or processor speed is measured against a "more accurate"
> system time? I mean, the GX was designed to be (near) 4MHz, so how can a
> built-in self-test tell anything else? Where does the self-test get the
> "absolute" time from?

The Yorke processor contains a cesium Clock for reference, which is
automatically synchronized via radio link with the US Bureau of Standards
Radio station WWV. I mean, the Bureau synchronizes to the HP48, not the
other way around.

Yeah, right.

The processor clock is derived from the 32kHz crystal using a phase-locked
loop. The software attempts to measure the processor clock using the
32kHz timing. I believe it uses interrupts to do so. The imprecision
in the reported speed (comparing one execution of the self-test to the
next) comes from the interrupt structure and the software implementation.
This part of the self test code is intended to verify that the phase-
locked loop (PLL) does not have gross errors in the way it multiplies
the frequency up from 32kHz.

In short, the processor clock and the 32kHz reference should have the
same level of inaccuracy, unless the PLL is broken. More inaccuracy
is introduced by the method of comparing the two. This is a gross
comparison only.

Off the topic, for those who care and missed the change in nomenclature:
the US National Bureau of Standards (NBS) is now apparently the NIST.
I think that spells out as National Institute of Science and Technology.
I was at a conference last week where everybody was talking about what
the NIST was doing. I finally admitted my ignorance and asked somebody
who or what was the NIST. Hmmm. Maybe next, we'll be going metric!
We'll have to spend Autumn Saturday afternoons watching the .25 back
of the 0.3-meter-ball team trying to get the ball past the 9.1m marker
to pick up a first down.

Dave.
-----
I don't speak for HP when I post here.
And HP doesn't speak for me.
Sounds pretty fair, eh?

[Giuseppe Donnini]

(02-10-2021 10:56 PM)Jonathan Busby Wrote:  NOTE #1 : The above reads like one only has to change the connections or other electrical properties of special pads on the Yorke SoC to "make" an S/SX or a G/GX, but that is not what I meant -- Instead, one only has to change the electrical properties ( eg. connections ) of the Yorke SoC's pads in order to transform the Yorke SoC into, what was for all intents and purposes, a Clarke-compatible SoC for an S/SX, *but* that only works for the SoC and not the rest of the calculator. The main PCB would still be completely different than the corresponding G/GX model, but, one would not need a Clarke SoC as the Yorke can be switched, by means already discussed, to a fully Clarke compatible mode that only runs at around 2MHz.

Thanks for pointing that out, Jonathan.

In view of the initial yield problems, it is immediately apparent why HP had to provide the Yorke chip with a dual speed option for the projected enhancement of the S series, but it may be less obvious why they continued to do so for the G series.

There are actually three reasons, as explained by Dave Arnett in another message sent to comp.sys.hp48 on October 15th, 1996 (Google Groups Link):

1. We were not certain whether there would be a demand for the 48SX after
the G and GX were introduced. I have jumpers on the board which would
allow you to build an HP48SX on this circuit board. That task requires
rerouting the card detect and select lines and (optionally) running the
CPU at 1X speed rather than 2X speed.

2. There were problems with the yield of Yorke ICs from NEC which would
run at 2X speed at all temperatures. We had a contingency plan that would
have made all HP48G units run at 1X speed until the problem was resolved.
The jumpers allowed us this option, had it been necessary. Thankfully,
the yield improved and we didn't have to exercice the option.

3. The old RAMBOX development systems used by the software team would
only support 1X operation. The ability to select 1X speed when runnig
code from the RAMBOXes, and then switch to 2X speed when running from the
EPROM was a design requirement. I saw no reason to delete this feature on
the production board. My EPROM unit and Charlie Patton's unit had a
gearshift for switching speed on the fly without a soldering iron.