HP-75C/D Processor Question

[Mike T.]

What processor was the HP-75C/D based on?

Since the HP75 supports IEEE floating point numbers I presume that it is has 64 bit registers unlike the 56 bit registers used the earlier machines.

The obvious candidate would be the Saturn processor, but this site says that the HP-71B was the first machine with the Saturn CPU and as this was released after the HP-75 this suggests that the HP75 used something else?

Just curious...

[Maximilian Hohmann]

Hello!

(03-07-2022 10:46 PM)Mike T. Wrote:  What processor was the HP-75C/D based on?

„Capricorn“: https://en.wikipedia.org/wiki/Capricorn_...processor)

Regards
Max

[rprosperi]

Capricorn is an 8-bit processor first used on the HP-85, and later on the -83, -85B, -86, -87 and -87XM desktop computers/calculators, and after the 75C, the 75D (which was barely different).

Also, while the 71B does support IEEE Math, the 75C does not. No 64-bit registers either, sorry.

The 75C HP-IL controller is not as capable (or as fast) as the 71B's contrioller, but it is often faster than the 71B for math/calculations.

[Thomas Klemm]

(03-08-2022 01:16 AM)rprosperi Wrote:  No 64-bit registers either, sorry.

But in the linked manual CPU STRUCTURE AND OPERATION on page 3-7 we find:

Quote:A multi-byte add with DRP set to 60 and ARP set to 50 (that is, executing ADM R60, R50) results in the 64-bit quantity starting with R50 being added to the 64-bit quantity starting with R60. The sum is stored in R60 through R67.

And then later on page 3-11:

\(
\begin{array}{c|c|c|}
\hline
\textbf{40} & \textbf{E1} & \textbf{E2} \\ \hline
\textbf{41} & \textbf{E0} & \textbf{MS} \\ \hline
\textbf{42} & \textbf{M10} & \textbf{M11} \\ \hline
\textbf{43} & \textbf{M8} & \textbf{M9} \\ \hline
\textbf{44} & \textbf{M6} & \textbf{M7} \\ \hline
\textbf{45} & \textbf{M4} & \textbf{M5} \\ \hline
\textbf{46} & \textbf{M2} & \textbf{M3} \\ \hline
\textbf{47} & \textbf{M0} & \textbf{M1} \\ \hline
\end{array}
\)

Quote:In real or floating-point format, the mantissa is a 12-digit quantity expressed as a magnitude. Each digit consists of four bits. The least significant digit, represented by M11, is stored in R42. The most significant digit, represented by M0, is stored in R47. The number is normalized; thus, there is an implied decimal point between M0 and M1 in R47. The sign of the mantissa is stored in the least significant digit of R41. A zero is stored as the sign of the mantissa if the number is positive; otherwise, a nine is stored. The exponent is a three-digit number stored in R40 and in the most significant digit position of R41. Exponents are expressed in ten's complement form.

In the table of the Assembler Instruction Set on page C-4 we find e.g. for ADM DR, AR: 4+B Clock Cycles.
Thus it might be that under the hood the bytes are processed sequentially.

[Martin Hepperle]

Indeed, the Capricorn architecture supports register groups of 8 bytes = 64 bit length.
You can e.g. add two 64 bit integers with a single opcode.
And it has quite a lot of registers!

PUMD R70,+R12
for example pushes 8 bytes in one go to the stack addressed by R12

ADM R70,R60
adds the 8 bytes in R60-67 to the bytes in R70-R77 in a single operation.
ADM R76,R66
adds only 2 bytes in R66-67 to the bytes in R77-R77 in a single operation.

And you could do that in binary as well as in BCD mode.

This /and the flexibility to address 1 to 8 bytes as one "register" was really outstanding for its time.

Another feature is the indirect addressing and the indirect-indirect addressing capability.
Most other processors at the time had to shuffle bytes between RAM and the few registers to achieve similar effects.

However, the external bus is 8 bits and the clock frequency usually rather low (about the same as an Apple II or an Epson HX-20).

One drawback is, that it did not have multiply or divide opcodes.