MLDL2000 trick

[MeindertKuipers]

One of the MLDL2000 users started to do some experiments with page 4 code, and found out that it does not always work in the MLDL2000, while it would work on Clonix devices.
After some tests I discovered that the 3.3V regulator does not always start in a very nice way, and that it would take longer for the power to stabilize in some specific cases. The effect was that the FPGA would take too much time to become active, and that the MLDL2000 would miss the access to page 4, and sometimes even giving corrupt data. Access to other pages in the HP41 is not problematic, as the HP41 takes more time internally to do things before first access of an external port.

For advanced users of the MLDL2000 who want to experiment with page 4, I have the following solutions:

• keep the MLDL2000 connected to the PC with USB. This will keep the FPGA powered
• bridge two pins on the power board (J7, connect 2 and 3). This slighly increases the power consumption, the FPGA is now powered when the HP41 is in standby, not only in run mode (which is the default)
• remove the bypass capacitor from the 3.3V regulator, this makes the regulator start much quicker, and seems not to have any other side effects.
  

[JurgenRo]

Hi Meindert! Thank you very much for the info - appreciate the continuing support of the amazing mldl2000!

Best, Juergen

[Sylvain Cote]

(02-27-2017 08:48 PM)JurgenRo Wrote:  Hi Meindert! Thank you very much for the info - appreciate the continuing support of the amazing mldl2000!

+1

Sylvain