Electronic Wizards

[brouhaha]

(12-19-2022 07:53 PM)Garth Wilson Wrote:  It'd be good if you could give some more information, like required speed, available power-supply voltages, etc.; but the easiest starting point that comes to mind is to just use an RS-232 line receiver.  (Keep in mind it will be inverting though.)  You could do a web search for terms like "logic voltage level translation."

It's a tricky problem and there are no good off-the-shelf solutions, because the world no longer uses negative voltage data or clock signals. There are a zillion different level converter chips available, none of which do what's needed here.

I'll offer my suggestions, with the warning that my analog design skills are nowhere near as good as my digital design skills.

I looked at using TIA-232 receivers, but I concluded that even the "fast" ones were probably too slow, and presented more input loading than I wanted. (I had input loading issues when connecting to some Spice series calculators, though those are NMOS.) My late friend and coconspirator Rich Ottosen recommended the ancient LM311 comparator, powered by external +/-15V supplies, and that worked well for connecting external electronics.

I've also used the LTC1045 hex comparator/level shifter, but the voltage range of the NMOS clock slightly exceeds the absolute maximum supply range for the PMOS clocks, so I only used that for the logic signals.

I think the easiest way to interface the PMOS clocks would be to use a logic-threshold nFET. The PMOS clock would drive the gate, obviously. The FET source would be tied to ground, and the FET drain would be the output, and have a fairly stiff pullup resistor, e.g. 1K or even less. It will act as an inverter, and when the PMOS clock exceeds 2V, will pull the output low. When the PMOS clock drops below 2V again, the nFET switches off, and the pullup will (more slowly) pull the output high.

The choice of nFET is non-critical, other than that it has to be specified for logic input (around 2V threshold). A beefy power FET is not recommended, as they have high gate capacitance. I think a BSS123 ought to be fine.

If you need totem-pole drive, i.e. to make the output transition at the trailing edge faster, or to avoid the current drawn by a pullup resistor, you might be able to add a pFET (e.g. BSS84), making it a CMOS inverter, but then you typically have both FETs briefly on simultaneously during the clock transitions (known as shoot-through), resulting in a huge current spike for the power supply.. One could put a resistor in series from each FET drain to the output to reduce that. In real CMOS ICs, the FET designs are highly optimized to prevent or minimize the problem.