Electronic Wizards

[teenix]

Just wondering if there are any of these on the Forum. I have been trying to solve a problem with a circuit but no luck so far. Happy to go PM or email if need be so it doesn't clutter the Forum.

I would like to convert the Classic -12V +6V clock signal to logic level but not having much success with valid signals.

cheers

Tony

[Garth Wilson]

It'd be good if you could give some more information, like required speed, available power-supply voltages, etc.; but the easiest starting point that comes to mind is to just use an RS-232 line receiver.  (Keep in mind it will be inverting though.)  You could do a web search for terms like "logic voltage level translation."

[brouhaha]

(12-19-2022 07:53 PM)Garth Wilson Wrote:  It'd be good if you could give some more information, like required speed, available power-supply voltages, etc.; but the easiest starting point that comes to mind is to just use an RS-232 line receiver.  (Keep in mind it will be inverting though.)  You could do a web search for terms like "logic voltage level translation."

It's a tricky problem and there are no good off-the-shelf solutions, because the world no longer uses negative voltage data or clock signals. There are a zillion different level converter chips available, none of which do what's needed here.

I'll offer my suggestions, with the warning that my analog design skills are nowhere near as good as my digital design skills.

I looked at using TIA-232 receivers, but I concluded that even the "fast" ones were probably too slow, and presented more input loading than I wanted. (I had input loading issues when connecting to some Spice series calculators, though those are NMOS.) My late friend and coconspirator Rich Ottosen recommended the ancient LM311 comparator, powered by external +/-15V supplies, and that worked well for connecting external electronics.

I've also used the LTC1045 hex comparator/level shifter, but the voltage range of the NMOS clock slightly exceeds the absolute maximum supply range for the PMOS clocks, so I only used that for the logic signals.

I think the easiest way to interface the PMOS clocks would be to use a logic-threshold nFET. The PMOS clock would drive the gate, obviously. The FET source would be tied to ground, and the FET drain would be the output, and have a fairly stiff pullup resistor, e.g. 1K or even less. It will act as an inverter, and when the PMOS clock exceeds 2V, will pull the output low. When the PMOS clock drops below 2V again, the nFET switches off, and the pullup will (more slowly) pull the output high.

The choice of nFET is non-critical, other than that it has to be specified for logic input (around 2V threshold). A beefy power FET is not recommended, as they have high gate capacitance. I think a BSS123 ought to be fine.

If you need totem-pole drive, i.e. to make the output transition at the trailing edge faster, or to avoid the current drawn by a pullup resistor, you might be able to add a pFET (e.g. BSS84), making it a CMOS inverter, but then you typically have both FETs briefly on simultaneously during the clock transitions (known as shoot-through), resulting in a huge current spike for the power supply.. One could put a resistor in series from each FET drain to the output to reduce that. In real CMOS ICs, the FET designs are highly optimized to prevent or minimize the problem.

[KeithB]

Have you thought about an opto-isolater?

[brouhaha]

A conventional optoisolator would put a LOT of load on the clock. Typical optoisolators require 5mA of input current. Low-current ones (e.g. Toshiba TLP182) still require 0.5mA, which is a lot to put on a MOS clock signal. There are various "digital isolators" using optical, capacitive, or magnetic technology, but they won't work with a >19V input swing.

One could use a buffer that can work on >19V (e.g. CD4049UB or CD4050B, 1uA input current) and have the buffer drive the opto, or any other sort of level shifter that might otherwise present undesirable loading on the PMOS clock. The 4049 and 4050 are only specified for 15V operation, but abs max is 20V, so they should work fine.

Another possibility is using capacitive coupling into a level shifter designed for positive input only, though the level shifter will still have to deal with a 19V input swing, which would usually require a supply voltage of at least 20V.

Maybe buffering with a CD4050B powered by the calculator, and using the output of that to drive a TIA-232 receiver as suggested by Garth Wilson, might be viable, though the prop delay through even a "fast" TIA-232 receiver can be huge.

Or use the CD4050B, put a voltage divider on its output to reduce swing to what's needed (maybe 3V), and capacitively couple that into the modern logic input.

I think I'd stil luse the nFET, though.

[teenix]

Thanks for the answers :-)

I tried a simple N FET buffer (2N7000). It worked at low frequency but not at 200 odd KHz, although breadboarded with flying leads probably not good. I was a bit worried about the gate switching currents on the clock source. It is hard to test different parts due to high postage rates to source them. I tried a few diode types but slow signal response and also faster Schottky but passed negative voltage

I actually posted this to an electronics Forum before thinking that there are some very smart people here so as it is calculator related in a way, maybe worth posting here.

I got this circuit from someone last night with scope traces showing that it works, so it is worth a try.

Another choice that came up was 3 resistors connected as a voltage summer, (superposition), but may load the clock source.

Space on a circuit board is very limited so the smaller the circuit the better, although I can sandwich two boards if that is required.

cheers

Tony

[brouhaha]

I'm increasingly of the opinion that puting a CD4049UB or CD4050B before the actual level shifter is a good idea. Here are the circuits I've tried in simulation, one with just the nFET and pullup, and one CMOS. .asc files of the schematics for LTspice also attached.

[brouhaha]

I should have put the net label CLK_PMOS on the other side of R1.
One can also increase the value of R1 by quite a bit. 1K is fine, above 2.2K it works less well. That reduces the peak current into the FET gates, but makes the FET take longer to turn on, so the current is drawn for a longer time. That's probably better for the clock driver in the calculator (in the ACT chip), but it's still not great, compared to buffering with a CD4xxxB.